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Details, datasheet, quote on part number:AD7868AQ
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Datasheet text preview:
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FEATURES Complete 12-Bit I/O System, Comprising: 12-Bit ADC with Track/Hold Amplifier 83 kHz Throughout Rate 72 dB SNR 12-Bit DAC with Output Amplifier 3 s Settling Time 72 dB SNR On-Chip Voltage Reference Operates from 5 V Supplies Low Power 130 mW typ Small 0.3" Wide DIP APPLICATIONS Digital Signal Processing Speech Recognition and Synthesis Spectrum Analysis High Speed Modems DSP Servo Control
LC2MOS Complete, 12-Bit Analog I/O System AD7868
FUNCTIONAL BLOCK DIAGRAM
VDD RI DAC R R
LDAC TFS TCLK DT CONTROL RFS RCLK DR CLK CONVST CLOCK
12-BIT DAC DAC 3V REFERENCE ADC 3V REFERENCE ADC SERIAL INTERFACE R 12-BIT ADC R
VOUT
DAC SERIAL INTERFACE
RO DAC
RO ADC
VIN TRACK/HOLD
AD7868
GENERAL DESCRIPTION
DGND
VSS
AGND
The AD7868 is a complete 12-bit I/O system containing a DAC and an ADC . The ADC is a successive approximation type with a track-and-hold amplifier having a combined throughput rate of 83 kHz. The DAC has an output buffer amplifier with a settling time of 3 µs to 12 bits. Temperature compensated 3 V buried Zener references provide precision references for the DAC and ADC. Interfacing to both the DAC and ADC is serial, minimizing pin count and giving a small 24-pin package size. Standard control signals allow serial interfacing to most DSP machines. Asynchronous ADC conversion control and DAC updating is made possible with the CONVST and LDAC logic inputs. The AD7868 operates from ± 5 V power supplies, the analog input/output range of the ADC/DAC is ± 3 V. The part is fully specified for dynamic parameters such as signal-to-noise ratio and harmonic distortion as well as traditional dc specifications. The part is available in a 24-pin, 0.3" wide, plastic or hermetic dual-in-line package (DIP) and in a 28-pin, plastic SOIC package.
PRODUCT HIGHLIGHTS
1. Complete 12-Bit I/O System. The AD7868 contains a 12-bit ADC with a track-and-hold amplifier and a 12-bit DAC with output amplifier. Also included are separate on-chip voltage references for the DAC and the ADC. 2. Dynamic Specifications for DSP Users. In addition to traditional dc specifications, the AD7868 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. These parameters along with important timing parameters are tested on every device. 3. Small Package. The AD7868 is available in a 24-pin DIP and a 28-pin SOIC package.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7868SPE= +5FICATI= 5 VS 5%, AGND = DGND = 0 V, f CI V 5%, V ON (V
ADC SECTION
DD SS
CLK
= 2.0 MHz external. All specifications TMIN to TMAX-
unless otherwise noted.)
A Version1
2
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3, 4 (SNR) @ +25°C TMIN to TMAX Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time DC ACCURACY Resolution Minimum Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Gain Error5 Negative Gain Error5 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT6 RO ADC @ +25°C RO ADC TC RO ADC TC Reference Load Sensitivity (RO ADC vs. I)
B Version1 72 71 78 78 78 80 2 12 12 ± 12 ±1 ± 0.9 ±5 ±5 ±5 ±3 ±1
T Version1 70 70 76 76 76 78 2 12 12 ± 12 ±1 ± 0.9 ±5 ±5 ±5 ±3 ±1 2.99/3.01 ± 25 ± 50 1.5
Units dB min dB min dB max dB max dB max dB max µs max Bits Bits LSB typ LSB max LSB max LSB max LSB max LSB max Volts mA max V min/V max ppm/°C typ ppm/°C max mV max
Test Conditions/Comments VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB for 0 < VIN < 41.5 kHz VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB for 0 < VIN < 41.5 kHz VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB for 0 < VIN < 41.5 kHz fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
70 70 78 78 78 80 2 12 12 ± 12 ± 0.9 ±5 ±5 ±5 ±3 ±1
No Missing Codes Are Guaranteed
2.99/3.01 2.99/3.01 ± 25 ± 25 ± 40 1.5 1.5
Reference Load Current Change (0 µA500 µA), Reference Load Should Not Be Changed During Conversion VDD = 5 V ± 5% VDD = 5 V ± 5% VIN = 0 V to VDD VIN = VSS to DGND
LOGIC INPUTS (CONVST, CLK, CONTROL) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Current7 (CONTROL Input Only) Input Capacitance, CIN8 LOGIC OUTPUTS DR, RFS Outputs Output Low Voltage, VOL RCLK Output Output Low Voltage, VOL DR, RFS, RCLK Outputs Floating-State Leakage Current Floating-State Output Capacitance8 CONVERSION TIME External Clock Internal Clock POWER REQUIREMENTS VD D VS S IDD I SS Total Power Dissipation
2.4 0.8 ± 10 ± 10 10
2.4 0.8 ± 10 ± 10 10
2.4 0.8 ± 10 ± 10 10
V min V max µA max µA max pF max
0.4 0.4 ± 10 15 10 10 +5 5 22 12 170
0.4 0.4 ± 10 15 10 10 +5 5 22 12 170
0.4 0.4 ± 10 15 10 10 +5 5 25 13 190
V max V max µA max pF max µs max µs max V nom V nom mA max mA max mW max
ISINK = 1.6 mA, Pull-Up Resistor = 4.7 k ISINK = 2.6 mA, Pull-Up Resistor = 2 k
The Internal Clock Has a Nominal Value of 2.0 MHz For Both DAC and ADC ± 5% for Specified Performance ± 5% for Specified Performance Cumulative Current from the Two VDD Pins Cumulative Current from the Two VSS Pins Typically 130 mW
NOTES 1 Temperature ranges are as follows: A/B Versions, 40°C to +85°C; T Version, 55°C to +125°C. 2 V IN = ± 3 V 3 SNR calculation includes distortion and noise components. 4 SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ. 5 Measured with respect to internal reference. 6 For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section). 7 Tying the CONTROL input to V DD places the device in a factory test mode where normal operation is not exhibited. 8 Sample tested @ +25°C to ensure compliance. Specifications subject to change without notice.
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REV. B
AD7868 DAC SECTION
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio3 (SNR) @ +25°C TMIN to TMAX Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise DC ACCURACY Resolution Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full-Scale Error5 Negative Full-Scale Error5 REFERENCE OUTPUT6 RO ADC @ +25°C RO ADC TC RO ADC TC Reference Load Change (RO DAC vs. I) REFERENCE INPUT RI DAC Input Range Input Current LOGIC INPUTS (LDAC, TFS, TCLK, DT) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN7 ANALOG INPUT Output Voltage Range dc Output Impedance Short-Circuit Current AC CHARACTERISTICS7 Voltage Output Settling-Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse Digital Feedthrough VIN to VOUT Isolation POWER REQUIREMENTS
2
(VDD = +5 V 5%, VSS = 5 V 5%, AGND = DGND = 0 V, RI DAC = +3 V and decoupled as shown in Figure 2, VOUT Load to AGND; RL = 2 k, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
A Version1 70 70 78 78 B Version1 72 71 78 78 T Version1 70 70 76 76 Units dB min dB min dB max dB max Test Conditions/Comments VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz Typically 71.5 dB at +25°C for 0 < VOUT < 20 kHz4 VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz Typically 84 dB at +25°C for 0 < VOUT < 20 kHz4 VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz Typically 84 dB at +25°C for 0 < VOUT < 20 kHz4
12 ± 1/2 ± 0.9 ±5 ±5 ±5
12 ± 1/2 ±1 ± 0.9 ±5 ±5 ±5
12 ± 1/2 ±1 ± 0.9 ±5 ±5 ±5 2.99/3.01 ± 25 ± 50 1.5
Bits LSB typ LSB max LSB max LSB max LSB max LSB max
Guaranteed Monotonic
2.99/3.01 2.99/3.01 ± 25 ± 25 ± 40 1.5 1.5
V min/V max ppm/°C typ ppm/°C max mV max Reference Load Current Change (0500 µA) V min/V max 3 V ± 5% µA max V min V max µA max pF max V nom typ mA typ Settling Time to Within ± 1/2 LSB of Final Value Typically 2 µs Typically 2.5 µs DAC Code Change All 1s to All 0s VIN = ± 3 V, 41.5 kHz Sine Wave VDD = 5 V ± 5% VDD = 5 V ± 5% VIN = 0 V to VDD
2.85/3.15 2.85/3.15 2.85/3.15 1 1 1 2.4 0.8 ± 10 10 ±3 0.3 20 2.4 0.8 ± 10 10 ±3 0.3 20 2.4 0.8 ± 10 10 ±3 0.3 20
3 3 10 2 100
3 3 10 2 100
3 3 10 2 100
µs max µs max nV secs typ nV secs typ dB typ
As per ADC Section
NOTES 1 Temperature ranges are as follows: A/B Versions, 40°C to +85°C; T Version, 55°C to +125°C. 2 VOUT (pkpk) = ± 3 V. 3 SNR calculation includes distortion and noise components. 4 Using external sample and hold. 5 Measured with respect to RI DAC and includes bipolar offset error. 6 For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section). 7 Sample tested @ +25°C to ensure compliance. Model Specifications subject to change without notice.
ORDERING GUIDE
Temperature Range
40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C 40°C to +85°C
SNR
70 dB 70 dB 72 dB 72 dB 70 dB 72 dB
Relative Accuracy (LSB)
± 1/2 typ ± 1/2 typ ± 1 max ± 1 max ± 1/2 typ ± 1 max
Package Option*
N-24 Q-24 N-24 Q-24 R-28 R-28
AD7868AN AD7868AQ AD7868BN AD7868BQ AD7868AR AD7868BR
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline IC).
REV. B
3
AD7868 TIMING CHARACTERISTICS1, 2 (V
Parameter ADC TIMING t1 t2 3 t3 t4 t5 4 t6 t13 5 DAC TIMING t7 t8 t9 6 t10 t11 t12 Limit at TMIN, TMAX (A, B Versions) 50 440 100 20 100 155 4 100 2 RCLK +200 to 3 RCLK + 200 50 75 150 30 75 40
DD
= +5 V
5%, VSS = 5 V
5%, AGND = DGND = 0 V)
Units ns min ns min ns min ns min ns max ns max ns min ns max ns typ Conditions/Comments CONVST Pulse Width RCLK Cycle Time, Internal Clock RFS to RCLK Falling Edge Setup Time RCLK Rising Edge to RFS RCLK to Valid Data Delay, CL = 35 pF Bus Relinquish Time after RCLK CONVST to RFS Delay
Limit at TMIN, TMAX (T Version) 50 440 100 20 100 155 4 100 2 RCLK +200 to 3 RCLK + 200 50 100 200 40 100 40
ns min ns min ns min ns min ns min ns min
TFS to TCLK Falling Edge TCLK Falling Edge to TFS TCLK Cycle Time Data Valid to TCLK Setup Time Data Valid to TCLK Hold Time LDAC Pulse Width
NOTES 1 Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 Serial timing is measured with a 4.7 k pull-up resistor on DR and RFS and a 2 k pull-up resistor on RCLK . The capacitance on all three output is 35 pF. 3 When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio = external clock mark/space ratio. 4 DR will drive higher capacitance loads but this will add to t 5 since it increases the external RC time constant (4.7 k/CL) and hence the time to reach 2.4 V. 5 Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization. 6 TCLK mark/space ratio is 40/60 to 60/40.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
PIN CONFIGURATIONS DIP
CONVST CLK RFS RCLK DR DGND VDD AGND VOUT 1 2 3 4 5 6 7 8 9 24 CONTROL 23 VDD 22 VSS 21 VIN 20 RO ADC
CONVST CLK RFS NC RCLK 1 2 3 4 5 6 7 8 9
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 7 V AGND to DGND . . . . . . . . . . . . . . . . . 0.3 V to VDD +0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD VIN to AGND . . . . . . . . . . . . . . . . VSS 0.3 V to VDD + 0.3 V RO ADC to AGND . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V RO DAC to AGND . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V RI DAC to AGND . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Digital Inputs to AGND . . . . . . . . . . . 0.3 V to VDD + 0.3 V Digital Outputs to AGND . . . . . . . . . . 0.3 V to VDD + 0.3 V Operating Temperature Range A, B Versions . . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C T Version . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SOIC
28 27 26 25 24 23 CONTROL VDD VSS NC VIN RO ADC AGND DGND TCLK NC NC DT TFS LDAC
AD7868
TOP VIEW (Not to Scale)
19 AGND 18 NC
DR DGND VDD
AD7868
TOP VIEW (Not to Scale)
22 21 20 19 18 17 16 15
17 DGND
AGND
16 TCLK 15 DT 14 TFS 13 LDAC NC = NO CONNECT
VOUT 10 NC 11 VSS 12 RO DAC 13
VSS 10 RO DAC 11 RI DAC 12
RI DAC 14 NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7868 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. B
AD7868
PIN FUNCTION DESCRIPTION
DIP Pin Number
Mnemonic
Function Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together. Negative Power Supply, 5 V ± 5%. Both VSS pins must be tied together. Analog Ground. Both AGND pins must be tied together. Digital Ground. Both DGND pins must be tied together.
POWER SUPPLY 7 & 23 V DD 10 & 22 V SS 8 & 19 AGND 6 &17 DGND
ANALOG SIGNAL AND REFERENCE 21 V IN ADC Analog Input. The ADC input range is ± 3 V. 9 V OUT Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, ± 3 V with RI DAC = +3 V. 20 RO ADC Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 µA. 11 RO DAC DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 µA. 12 RI DAC DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7868 is 3 V. ADC INTERFACE AND CONTROL 2 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying pin to VSS enables the internal laser-trimmed oscillator. RFS Receive Frame Synchronization, Logic Output. This is an active low open-drain output which provides 3 a framing pulse for serial data. An external 4.7 k pull-up resistor is required on RFS. 4 RCLK Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal or external ADC clock. If the CONTROL input is at VSS the clock runs continuously. With the CONTROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is complete. RCLK is an open-drain output and requires an external 2 k pull-up resistor. 5 DR Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 k resistor is required on the DR output. 1 CONVST Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold mode and starts an ADC conversion. This input in asynchronous to the CLK input. 24 CONTROL Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at 5 V, the RCLK is continuous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited. DAC INTERFACE AND CONTROL 14 TFS Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial data expected after the falling edge of this signal. 15 DT Transmit Data, Logic Input. This is the data input which is used in conjunction with TFS and TCLK to transfer serial data to the input latch. 16 TCLK Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low. LDAC Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the 13 falling edge of this signal. 18 NC No Connect.
REV. B
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