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Details, datasheet, quote on part number:AD7888BRU
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| Part: | AD7888BRU |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit |
| Description: | 2.7 V to 5.25 V, Micro Power, 8-Channel, 125 Ksps, 12-Bit ADC in 16-Pin Tssop |
| Company: | Analog Devices |
| Datasheet: | Download AD7888BRU datasheet File size : 179 kB |
| Request For quote: | Find where to buy AD7888BRU
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Datasheet text preview:
a
2.7 V to 5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP AD7888
FUNCTIONAL BLOCK DIAGRAM
AIN1 AIN8 2.5V REF REF IN/REF OUT BUF
FEATURES Specified for VDD of 2.7 V to 5.25 V Flexible Power/Throughput Rate Management Shutdown Mode: 1 A Max Eight Single-Ended Inputs Serial Interface: SPITM/QSPITM/MICROWIRETM/DSP Compatible 16-Lead Narrow SOIC and TSSOP Packages APPLICATIONS Battery-Powered Systems (Personal Digital Assistants, Medical Instruments, Mobile Communications) Instrumentation and Control Systems High-Speed Modems
AD7888
I/P MUX T/H VDD
COMP
CHARGE REDISTRIBUTION DAC
SAR + ADC CONTROL LOGIC
GENERAL DESCRIPTION
AGND SPORT
AGND
The AD7888 is a high speed, low power, 12-bit ADC that operates from a single 2.7 V to 5.25 V power supply. The AD7888 is capable of a 125 kSPS throughput rate. The input track-andhold acquires a signal in 500 ns and features a single-ended sampling scheme. The AD7888 contains eight single-ended analog inputs, AIN1 through AIN8. The analog input on each of these channels is from 0 to VREF. The part is capable of converting full power signals up to 2.5 MHz. The AD7888 features an on-chip 2.5 V reference that can be used as the reference source for the A/D converter. The REF IN/REF OUT pin allows the user access to this reference. Alternatively, this pin can be overdriven to provide an external reference voltage for the AD7888. The voltage range for this external reference is from 1.2 V to VDD. CMOS construction ensures low power dissipation of typically 2 mW for normal operation and 3 µW in power-down mode. The part is available in a 16-lead narrow body small outline (SOIC) and a 16-lead thin shrink small outline (TSSOP) package.
CS
DIN
DOUT
SCLK
PRODUCT HIGHLIGHTS
1. Smallest 12-bit 8-channel ADC; 16-lead TSSOP is the same area as an 8-lead SOIC and less than half the height. 2. Lowest Power 12-bit 8-channel ADC. 3. Flexible power management options including automatic power-down after conversion. 4. Analog input range from 0 V to VREF (VDD). 5. Versatile serial I/O port (SPI/QSPI/MICROWIRE/DSP Compatible).
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
(VDD = 2.7 V to 5.25 V, REFIN/REFOUT = 2.5 V External/Internal Reference unless otherwise noted; fSCLK = 2 MHz (VDD = 2.7 V to 5.25 V); TA = TMIN to TMAX, unless otherwise noted.)
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion Ratio2, 3 (SNR) Total Harmonic Distortion2 (THD) Peak Harmonic or Spurious Noise2 Intermodulation Distortion2 (IMD) Second Order Terms Third Order Terms Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Offset Error Offset Error Match2 Gain Error2 Gain Error Match2 ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT REFIN Input Voltage Range Input Impedance REFOUT Output Voltage REFOUT Tempco LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Throughput Time Track/Hold Acquisition Time2 Conversion Time VDD 0.5 VDD 0.5 0.4 0.4 ± 10 ± 10 10 10 Straight (Natural) Binary 16 1.5 14.5 16 1.5 14.5 V min V max µA max pF max A Version1 71 80 80 78 78 80 2.5 12 ±2 ±2 ±6 ± 4.5 2 ±2 3 0 to VREF ±1 38 4 2 . 5 / VD D 5 2.45/2.55 ± 50 2.4 2.1 0.8 ± 10 10 B Version1 71 80 80 78 78 80 2.5 12 ±1 1/+1.5 ±6 ± 4.5 2 ±2 3 0 to VREF ±1 38 4 2 . 5 / VD D 5 2.45/2.55 ± 50 2.4 2.1 0.8 ± 10 10 Unit dB typ dB typ dB typ dB typ dB typ dB typ MHz typ Bits LSB max LSB max LSB max LSB max LSB typ LSB max LSB max Volts µA max pF typ pF typ V min/max k typ V min/max ppm/°C typ V min V min V max µA max pF max Test Condition/Comment fIN = 10 kHz Sine Wave, fSAMPLE = 125 kSPS fIN = 10 kHz Sine Wave, fSAMPLE = 125 kSPS fIN = 10 kHz Sine Wave, fSAMPLE = 125 kSPS fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 125 kSPS fa = 9.983 kHz, fb = 10.05 kHz, fSAMPLE = 125 kSPS fIN = 25 kHz @ 3 dB Any Channel
AD7888SPECIFICATIONS
Guaranteed No Missed Codes to 11 Bits (A Grade) Guaranteed No Missed Codes to 12 Bits (B Grade) VDD = 4.75 V to 5.25 V (Typically ± 3 LSB) VDD = 2.7 V to 3.6 V (Typically ± 2 LSB) Typically 30 LSB with Internal Reference
When in Track When in Hold Functional from 1.2 V Very High Impedance If Internal Reference Disabled
VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V VDD = 2.7 V to 5.25 V Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 µA VDD = 2.7 V to 5.25 V ISINK = 200 µA
SCLK Cycles SCLK Cycles SCLK Cycles
Conversion Time + Acquisition Time. 125 kSPS with 2 MHz Clock 7.25 µs (2 MHz Clock)
2
REV. B
AD7888
Parameter POWER REQUIREMENTS VD D IDD Normal Mode5 (Static) Normal Mode (Operational) Using Standby Mode Using Shutdown Mode Standby Mode6 Shutdown Mode6 Normal-Mode Power Dissipation Shutdown Power Dissipation Standby Power Dissipation A Version 2.7/5.25 700 700 450 80 12 200 2 1 3.5 2.1 10 3 1 600
1
B Version 2.7/5.25 700 700 450 80 12 200 2 1 3.5 2.1 10 3 1 600
1
Unit V min/max µA max µA typ µA typ µA typ µA typ µA max µA max µA max mW max mW max µW max µW max mW max µW max
Test Condition/Comment
fSAMPLE = 125 kSPS fSAMPLE = 50 kSPS fSAMPLE = 10 kSPS fSAMPLE = 1 kSPS VDD = 2.7 V to 5.25 V VDD = 4.75 V to 5.25 V (0.5 µA typ) VDD = 2.7 V to 3.6 V VDD = 5 V VD D = 3 V VD D = 5 V VD D = 3 V VD D = 5 V VD D = 3 V
NOTES 1 Temperature ranges as follows: A Version: 40°C to +105°C; B Version: 40°C to +105°C. 2 See Terminology. 3 SNR calculation includes distortion and noise components. 4 Sample tested @ 25°C to ensure compliance. 5 All digital inputs @ GND except CS @ VDD. No load on the digital outputs. Analog inputs @ GND. 6 SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ VDD. No load on the digital outputs. Analog inputs @ GND. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
ORDERING GUIDE Linearity Error Package (LSB)1 Description ±2 ±1 ±2 ±1 SOIC SOIC TSSOP TSSOP Package Option R-16A R-16A RU-16 RU-16
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V Analog Input Voltage to AGND . . . . . 0.3 V to VDD + 0.3 V Digital Input Voltage to AGND . . . . . . 0.3 V to VDD + 0.3 V Digital Output Voltage to AGND . . . . 0.3 V to VDD + 0.3 V REFIN/REFOUT to AGND . . . . . . . . 0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA Operating Temperature Range Commercial (A Version) . . . . . . . . . . . . . . . . . . . . . . 40°C to +105°C (B Version) . . . . . . . . . . . . . . . . . . . . . . . 0°C to +105°C Storage Temperature Range . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C SOIC, TSSOP Package, Power Dissipation . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . 124.9°C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP) JC Thermal Impedance . . . . . . . . . . . . . 42.9°C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
Model AD7888AR AD7888BR AD7888ARU AD7888BRU EVAL-AD7888CB 2 EVAL-CONTROL BRD23
NOTES 1 Linearity error here refers to integral linearity error. 2 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7888 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
3
AD7888 TIMING SPECIFICATIONS1 (T = T
A
MIN
to TMAX, unless otherwise noted)
Parameter f SCLK tCONVERT tACQ t1 t2 3 t3 3 t4 t5 t6 t7 t8 4 t9
2
Limit at TMIN, TMAX (A, B Versions) 4.75 V to 5.25 V 2.7 V to 3.6 V 2 14.5 tSCLK 1 . 5 tS C L K 10 30 75 20 20 0 . 4 tS C L K 0 . 4 tS C L K 80 5 2 14.5 tSCLK 1 . 5 tS C L K 10 60 100 20 20 0 . 4 tS C L K 0 . 4 tS C L K 80 5
Unit MHz max
Description
ns min ns max ns max ns min ns min ns min ns min ns max µs typ
Throughput Time = tCONVERT + tACQ = 16 tSCLK CS to SCLK Setup Time Delay from CS until DOUT 3-State Disabled Data Access Time after SCLK Falling Edge Data Setup Time Prior to SCLK Rising Edge Data Valid to SCLK Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge to DOUT High Impedance Power-Up Time from Shutdown
NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10% and time for an output to cross 0.4 V or 2.0 V with V DD = 3 V ± 10%. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice.
200 A
IOL
TO OUTPUT PIN
1.6V CL 50pF
200 A
IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
4
REV. B
AD7888
PIN CONFIGURATIONS SOIC AND TSSOP
CS
1 16 SCLK 15 DOUT 14 DIN
REF IN/REF OUT 2 VD D 3 AGND 4
AD7888
TOP VIEW
13 AGND
AIN1 5 (Not to Scale) 12 AIN8 AIN2 6 AIN3 7 AIN4 8
11 AIN7 10 AIN6 9
AIN5
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2
Mnemonic CS REF IN/REF OUT
Function Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7888 and also frames the serial data transfer. Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888. Alternatively, the internal reference can be disabled and an external reference applied to this input. The voltage range for the external reference is from 1.2 V to VDD. Power Supply Input. The VDD range for the AD7888 is from 2.7 V to 5.25 V. Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and any external reference signals should be referred to this AGND voltage. Both of these pins should connect to the AGND plane of a system. Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0 through ADD2 bits of the Control Register. The input range for all input channels is 0 to VREF. Any unused input channels should be connected to AGND to avoid noise pickup. Data In. Logic Input. Data to be written to the AD7888's Control Register is provided on this input and is clocked into the register on the rising edge of SCLK (see Control Register section). Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial data to the Control Register. This clock input is also used as the clock source for the AD7888's conversion process.
3 4, 13
V DD AGND
512
AIN1AIN8
14 15
DIN DOUT
16
SCLK
REV. B
5
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