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Details, datasheet, quote on part number:AD7920SNR
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Datasheet text preview:
250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 AD7910/AD7920
FEATURES Throughput Rate: 250 kSPS Specified for VDD of 2.35 V to 5.25 V Low Power: 3.6 mW Typ at 250 kSPS with 3 V Supplies 12.5 mW Typ at 250 kSPS with 5 V Supplies Wide Input Bandwidth: 71 dB SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Standby Mode: 1 A Max 6-Lead SC70 Package 8-Lead MSOP Package APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High Speed Modems Optical Sensors FUNCTIONAL BLOCK DIAGRAM
VDD
VIN
T/H
10-/12-BIT SUCCESSIVE APPROXIMATION ADC
SCLK CONTROL LOGIC SDATA CS
AD7910/ AD7920
GND
The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK.
PRODUCT HIGHLIGHTS
1. 10-/12-Bit ADCs in SC70 and MSOP Packages.
GENERAL DESCRIPTION
2. Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when Power-Down mode is used while not converting. The part also features a Power-Down mode to maximize power efficiency at lower throughput rates. Current consumption is 1 A max and 50 nA typically when in Power-Down mode. 4. Reference derived from the power supply. 5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
The AD7910/AD7920 are respectively 10-bit and 12-bit, high speed, low power, successive approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 250 kSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7910/AD7920 use advanced design techniques to achieve very low power dissipation at high throughput rates.
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V to 5.25 r ise AD7910SPECIFICATIONS1 o(Vthe=w2.35noted.) V, f
DD
SCLK =
5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error3, 4 Gain Error3, 4 Total Unadjusted Error (TUE)3, 4 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation6 Normal Mode (Operational) Full Power-Down
A Grade1, 2 61 72 73 82 82 10 30 13.5 2 10 ± 0.5 ± 0.5 ±1 ±1 ± 1.2 0 to VDD ± 0.5 20 2.4 0.8 0.4 ± 0.5 ± 10 5
Unit dB min dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max V µA max pF typ V min V max V max µA max nA typ pF max
Test Conditions/Comments fIN = 100 kHz Sine Wave
fa = 100.73 kHz, fb = 90.7 kHz fa = 100.73 kHz, fb = 90.7 kHz
@ 3 dB @ 0.1 dB
Guaranteed No Missed Codes to 10 Bits
Track-and-Hold in Track, 6 pF typ when in Hold
VDD = 5 V VDD = 3 V Typically 10 nA, VIN = 0 V or VDD
VDD 0.2 V min 0.4 V max ±1 µA max 5 pF max Straight (Natural) Binary 2.8 250 250 2.35/5.25 2.5 1.2 3 1.4 1 15 4.2 5 3 µs max ns max kSPS max V min/max mA typ mA typ mA max mA max µA max mW max mW max µW max µW max
ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V ISINK = 200 µA
14 SCLK cycles with SCLK at 5 MHz
Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK On or Off VDD = 2.35 V to 3.6 V, SCLK On or Off VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Typically 50 nA VDD = 5 V, fSAMPLE = 250 kSPS VDD = 3 V, fSAMPLE = 250 kSPS VDD = 5 V VDD = 3 V
NOTES 1 Temperature range from 40°C to +85°C. 2 Operational from V DD = 2.0 V, with input high voltage (V INH) 1.8 V min. 3 See Terminology section. 4 SC70 values guaranteed by characterization. 5 Sample tested @ 25°C to ensure compliance. 6 See Power Versus Throughput Rate section. Specifications subject to change without notice.
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V to 5.25 AD7920SPECIFICATIONS1 (oVthe=w2.35noted.) V, f r ise
DD SCLK =
5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
Test Conditions/Comments fIN = 100 kHz Sine Wave VDD = 2.35 V to 3.6 V, TA = 25oC VDD = 2.4 V to 3.6 V VDD = 2.35 V to 3.6 V VDD = 4.75 V to 5.25 V, TA = 25oC VDD = 4.75 V to 5.25 V VDD = 2.35 V to 3.6 V, TA = 25oC VDD = 2.4 V to 3.6 V VDD = 4.75 V to 5.25 V, TA = 25oC VDD = 4.75 V to 5.25 V
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)3
A Grade1, 2 B Grade1, 2 Unit 70 69 71.5 69 68 71 70 70 69 80 82 84 84 10 30 13.5 2 12 ± 0.75 70 69 71.5 69 68 71 70 70 69 80 82 84 84 10 30 13.5 2 12 ± 1.5 0.9/+1.5 ± 0.75 ± 1.5 ± 1.5 ± 1.5 ± 0.2 ± 1.5 ± 0.5 ±2 0 to VDD ± 0.5 20 2.4 1.8 0.8 0.4 ± 0.5 ± 10 5 dB min dB min dB typ dB min dB min dB min dB min dB min dB min dB typ dB typ dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max V µA max pF typ V min V min V max V max µA max nA typ pF max V min V max µA max pF max
Signal-to-Noise Ratio (SNR)3
Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity Offset Error3, 5 Gain Error3, 5 Total Unadjusted Error (TUE)3,5 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN6 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance6 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate
fa = 100.73 kHz, fb = 90.72 kHz fa = 100.73 kHz, fb = 90.72 kHz
@ 3 dB @ 0.1 dB B Grade4
Guaranteed No Missed Codes to 12 Bits
0 to VDD ± 0.5 20 2.4 1.8 0.8 0.4 ± 0.5 ± 10 5
Track-and-Hold in Track, 6 pF typ when in Hold
VDD = 2.35 V VDD = 3.6 V to 5.25 V VDD = 2.35 V to 3.6 V Typically 10 nA, VIN = 0 V or VDD
VDD 0.2 VDD 0.2 0.4 0.4 ±1 ±1 5 5 Straight (Natural) Binary 3.2 250 250 3.2 250 250
ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V ISINK = 200 µA
µs max ns max kSPS max
16 SCLK Cycles with SCLK at 5 MHz See Serial Interface Section
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AD7910/AD7920 AD7920SPECIFICATIONS1 (continued)
Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation7 Normal Mode (Operational) Full Power-Down A Grade1, 2 2.35/5.25 2.5 1.2 3 1.4 1 15 4.2 5 3 B Grade1, 2 Unit 2.35/5.25 2.5 1.2 3 1.4 1 15 4.2 5 3 V min/max mA typ mA typ mA max mA max µA max mW max mW max µW max µW max Digital I/Ps = 0 V or VDD. VDD = 4.75 V to 5.25 V, SCLK On or Off VDD = 2.35 V to 3.6 V, SCLK On or Off VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS Typically 50 nA VDD = 5 V, fSAMPLE = 250 kSPS VDD = 3 V, fSAMPLE = 250 kSPS VDD = 5 V VDD = 3 V Test Conditions/Comments
NOTES 1 Temperature range from 40°C to +85°C. 2 Operational from V DD = 2.0 V, with input low voltage (V INL) 0.35 V max. 3 See Terminology Section. 4 B Grade, maximum specs apply as typical figures when V DD = 4.75 V to 5.25 V. 5 SC70 values guaranteed by characterization. 6 Sample tested @ 25°C to ensure compliance. 7 See Power Versus Throughput Rate section. Specifications subject to change without notice.
TIMING SPECIFICATIONS1
Parameter fSCLK
2
(VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Unit kHz min MHz max
3
AD7910/AD7920 Limit at TMIN, TMAX 10 5 14 16 50 10 10 22 40 0.4 0.4
Description
tCONVERT tQUIET t1 t2 t3 4 t4 4 t5 t6 t7 5
tSCLK tSCLK ns min ns min ns min ns max ns max ns min ns min ns min ns min ns min ns max ns min µs max
tSCLK t SCLK
t8 6 tPOWER-UP8
10 9.5 7 36 See Note 7 1
AD7910 AD7920 Minimum Quiet Time Required between Bus Relinquish and Start of Next Conversion Minimum CS Pulsewidth CS to SCLK Setup Time Delay from CS until SDATA Three-State Disabled Data Access Time after SCLK Falling Edge SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to Data Valid Hold Time VDD 3.3 V 3.3 V 3.6 V SCLK Falling Edge to SDATA Three-State SCLK Falling Edge to SDATA Three-State Power-Up Time from Full Power-Down
NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V DD = 2.35 V and 0.8 V or 2.0 V for V DD > 2.35 V. 5 Measured with a 50 pF load capacitor. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 t7 values apply to t 8 minimum values also. 8 See Power-Up Time section. Specifications subject to change without notice.
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200 A
TIMING EXAMPLES
IOL
Figures 2 and 3 show some of the timing parameters from the Timing Specifications table.
1.6V
TO OUTPUT PIN
CL 50pF 200 A IOH
Timing Example 1
Figure 1. Load Circuit for Digital Output Timing Specifications
From figure 3, having fSCLK = 5 MHz and a throughput rate of 250 kSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 µs. With t2 = 10 ns min, this leaves tACQ to be 1.49 µs. This 1.49 µs satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This allows a value of 954 ns for tQUIET, satisfying the minimum requirement of 50 ns.
t1
CS
t CONVERT t2
SCLK 1 2 3 4
t6
5 13
B
14 15 16
t5 t3
SDATA THREESTATE Z ZERO ZERO
t8 tQUIET
DB1 DB0
t4
ZERO DB11 4 LEADING ZEROS
t7
DB10 DB2
THREE-STATE
Figure 2. AD7920 Serial Interface Timing Diagram
CS
t CONVERT t2
SCLK 1 2 3 4 5 13
B
14
C
15 16
t8 tQUIET
12.5(1/fSCLK)
tACQ
1/THROUGHPUT
Figure 3. Serial Interface Timing Example
Timing Example 2
The AD7920 can also operate with slower clock frequencies. From Figure 3, having fSCLK = 3.4 MHz and a throughput rate of 150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 6.66 µs. With t2 = 10 ns min, this leaves tACQ to be 2.97 µs. This 2.97 µs satisfies the requirement of 250 ns for tACQ. From Figure 3, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max.
This allows a value of 2.19 µs for tQUIET satisfying the minimum requirement of 50 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 3.
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