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Details, datasheet, quote on part number:AD7927
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Datasheet text preview:
8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP AD7927
FEATURES Fast Throughput Rate: 200 kSPS Specified for AVDD of 2.7 V to 5.25 V Low Power: 3.6 mW Max at 200 kSPS with 3 V Supply 7.5 mW Max at 200 kSPS with 5 V Supply 8 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth: 70 dB Min SINAD at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/ MICROWIRETM/DSP Compatible Shutdown Mode: 0.5 A Max 20-Lead TSSOP Package FUNCTIONAL BLOCK DIAGRAM
AVDD REFIN VIN0 · · · · · · · · · · · · · VIN7
T/H 12-BIT SUCCESSIVE APPROXIMATION ADC I/P MUX
SCLK DOUT SEQUENCER CONTROL LOGIC DIN CS
GENERAL DESCRIPTION
The AD7927 is a 12-bit, high speed, low power, 8-channel, successive-approximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 200 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7927 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7927 consumes 1.2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 1.5 mA maximum. Through the configuration of the Control Register, the analog input range for the part can be selected as 0 V to REFIN or 0 V to 2 „ REFIN, with either straight binary or twos complement output coding. The AD7927 features eight single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7927 is determined by the SCLK frequency, as this is also used as the master clock to control the conversion. The conversion time may be as short as 800 ns with a 20 MHz SCLK. REV. 0
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AD7927
VDRIVE GND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption. The AD7927 offers up to 200 kSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7927 dissipates 3.6 mW of power maximum. 2. Eight Single-Ended Inputs with a Channel Sequencer. A consecutive sequence of channels, through which the ADC will cycle and convert on, can be selected. 3. Single-Supply Operation with VDRIVE Function. The AD7927 operates from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of AVDD. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 mA maximum when in full shutdown. 5. No Pipeline Delay. The part features a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7927SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 „ REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding 70 69 70 77 73 78 76 90 90 10 50 82 8.2 1.6
(AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
Unit dB min dB min dB min dB max dB max dB max dB max dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max V V mA max pF typ V mA max kW typ V min V max mA max pF max Test Conditions/Comments fIN = 50 kHz Sine Wave, fSCLK = 20 MHz @5V @ 3 V Typically 70 dB @ 5 V Typically 84 dB @ 3 V Typically 77 dB @ 5 V Typically 86 dB @ 3 V Typically 80 dB fa = 40.1 kHz, fb = 41.5 kHz
B Version1
fIN = 400 kHz @ 3 dB @ 0.1 dB
12 ±1 0.9/+1.5 ±8 ± 0.5 ± 1.5 ± 0.5 ± 1.5 ± 0.5 ±8 ± 0.5 ±1 ± 0.5 0 to REFIN 0 to 2 „ REFIN ±1 20 2.5 ±1 36 0 . 7 „ V DRIVE 0 . 3 „ V DRIVE ±1 10
Guaranteed No Missed Codes to 12 Bits Straight Binary Output Coding Typically ± 0.5 LSB
REFIN to +REFIN Biased about REFIN with Twos Complement Output Coding Typically ± 0.8 LSB
RANGE Bit Set to 1 RANGE Bit Set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V fSAMPLE = 200 kSPS ± 1% Specified Performance
Typically 10 nA, VIN = 0 V or VDRIVE
VDRIVE 0.2 V min 0.4 V max ±1 mA max 10 pF max Straight (Natural) Binary Twos Complement
ISOURCE = 200 mA, AVDD = 2.7 V to 5.25 V ISINK = 200 mA Coding Bit Set to 1 Coding Bit Set to 0
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Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS A V DD V DRIVE IDD4 During Conversion B Version1 800 300 300 200 2.7/5.25 2.7/5.25 Unit ns max ns max ns max kSPS max V min/max V min/max mA max mA max mA typ mA max mA max mA typ mA typ mA max mA max mW max mW max mW max mW max mW max mW max Digital I/Ps = 0 V or VDRIVE AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz AVDD = 2.7 V to 5.25 V, SCLK On or Off AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz SCLK On or Off (20 nA typ) SCLK On or Off (20 nA typ) AVDD = 5 V, fSCLK = 20 MHz AVDD = 3 V, fSCLK = 20 MHz A VDD = 5 V A VDD = 3 V A VDD = 5 V A VDD = 3 V Test Conditions/Comments 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section
2.7 2 Normal Mode (Static) 600 Normal Mode (Operational) fSAMPLE = 200 kSPS 1.5 1.2 Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900 650 Auto Shutdown (Static) 0.5 Full Shutdown Mode 0.5 Power Dissipation4 Normal Mode (Operational) 7.5 3.6 Auto Shutdown (Static) 2.5 1.5 Full Shutdown Mode 2.5 1.5
NOTES 1 Temperature ranges as follows: B Version: 40C to +85C. 2 See Terminology section. 3 Sample tested @ 25C to ensure compliance. 4 See Power versus Throughput Rate section. Specifications subject to change without notice.
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AD7927 TIMING SPECIFICATIONS1
Parameter f SCLK
2
(AVDD = 2.7 V to 5.25 V, VDRIVE
AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
Description
Limit at TMIN, TMAX AD7927 AVDD = 3 V AVDD = 5 V Unit 10 20 1 6 „ t SCLK 50 10 35 40 0 . 4 „ tSCLK 0 . 4 „ tSCLK 10 15/45 10 5 20 1 10 20 1 6 „ t SCLK 50 10 30 40 0 . 4 „ tSCLK 0 . 4 „ tSCLK 10 15/35 10 5 20 1 kHz min MHz max ns min ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min ms max
tCONVERT tQUIET t2 t3 3 t4 3 t5 t6 t7 t8 4 t9 t10 t11 t12
Minimum Quiet Time Required between CS Rising Edge and Start of Next Conversion CS to SCLK Setup Time Delay from CS until DOUT Three-State Disabled Data Access Time after SCLK Falling Edge SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to DOUT Valid Hold Time SCLK Falling Edge to DOUT High Impedance DIN Setup Time Prior to SCLK Falling Edge DIN Hold Time after SCLK Falling Edge Sixteenth SCLK Falling Edge to CS High Power-Up Time from Full Power-Down/Auto Shutdown Mode
NOTES 1 Sample tested at 25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 „ VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the timing characteristics t8, is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice.
200 A
IOL
TO OUTPUT PIN
CL 50pF 200 A
1.6V
IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
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ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C, unless otherwise noted.)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VDRIVE to AGND . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V Analog Input Voltage to AGND . . . . 0.3 V to AVDD + 0.3 V Digital Input Voltage to AGND . . . . . . . . . . . . 0.3 V to +7 V Digital Output Voltage to AGND . . . . . 0.3 V to AVDD + 0.3 V REFIN to AGND . . . . . . . . . . . . . . . . 0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA Operating Temperature Range Commercial (B Version) . . . . . . . . . . . . . . 40C to +85C Storage Temperature Range . . . . . . . . . . . 65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW qJA Thermal Impedance . . . . . . . . . . . . . . 143C/W (TSSOP) qJC Thermal Impedance . . . . . . . . . . . . . . . 45C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD7927BRU EVAL-AD7927CB2 EVAL-CONTROL BRD23
Temperature Range 40C to +85C
Linearity Error (LSB)1 ±1
Package Option RU-20
Package Description TSSOP Evaluation Board Controller Board
NOTES 1 Linearity error here refers to integral linearity error. 2 This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g., EVAL-AD7927CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Application Note for more information.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7927 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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