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Details, datasheet, quote on part number:AD8115AST
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| Part: | AD8115AST |
| Category: | Analog & Mixed-Signal Processing => Switches & Multiplexers => Analog Switches |
| Description: | Low Cost 225 MHZ 16 X 16 Crosspoint Switch, G=+2 |
| Company: | Analog Devices |
| Datasheet: | Download AD8115AST datasheet File size : 1644 kB |
| Request For quote: | Find where to buy AD8115AST
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Datasheet text preview:
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FEATURES 16 16 High-Speed Nonblocking Switch Arrays AD8114; G = +1 AD8115; G = +2 Serial or Parallel Programming of Switch Array Serial Data Out Allows "Daisy Chaining" of Multiple 16 16s to Create Larger Switch Arrays High Impedance Output Disable Allows Connection of Multiple Devices Without Loading the Output Bus For Smaller Arrays See Our AD8108/AD8109 (8 8) or AD8110/AD8111 (16 8) Switch Arrays Complete Solution Buffered Inputs Programmable High Impedance Outputs 16 Output Amplifiers, AD8114 (G = +1), AD8115 (G = +2) Drives 150 Loads Excellent Video Performance 25 MHz, 0.1 dB Gain Flatness 0.05%/0.05 Differential Gain/Differential Phase Error (RL = 150 ) Excellent AC Performance 3 dB Bandwidth: 225 MHz Slew Rate: 375 V/ s Low Power of 700 mW (2.75 mW per Point) Low All Hostile Crosstalk of 70 dB @ 5 MHz Reset Pin Allows Disabling of All Outputs (Connected Through a Capacitor to Ground Provides "Power-On" Reset Capability) 100-Lead LQFP Package (14 mm 14 mm) APPLICATIONS Routing of High-Speed Signals Including: Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed Video (MPEG, Wavelet) 3-Level Digital Video (HDB3) Datacomms Telecomms PRODUCT DESCRIPTION
16
Low Cost 225 MHz 16 Crosspoint Switches AD8114 /AD8115*
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4 A0 A1 A2 A3 80-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING 80 PARALLEL LATCH 80 16 DECODE 5:16 DECODERS OUTPUT BUFFER G = +1, G = +2 SET INDIVIDUAL OR RESET ALL OUTPUTS TO "OFF" 16 DATA OUT
CLK
DATA IN UPDATE CE RESET
AD8114/ AD8115
256
SWITCH MATRIX 16 INPUTS
ENABLE/DISABLE
16 OUTPUTS
The AD8114/AD8115 are high-speed 16 × 16 video crosspoint switch matrices. They offer a 3 dB signal bandwidth greater than 200 MHz and channel switch times of less than 50 ns with 1% settling. With 70 dB of crosstalk and 90 dB isolation (@ 5 MHz), the AD8114/AD8115 are useful in many high-speed applications. The differential gain and differential phase of better than 0.05% and 0.05° respectively, along with 0.1 dB flatness out to 25 MHz while driving a 75 back-terminated load, make the AD8114/ AD8115 ideal for all types of signal switching.
*Patent Pending.
The AD8114/AD8115 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off channels do not load the output bus. The AD8114 has a gain of +1, while the AD8115 offers a gain of +2. They operate on voltage supplies of ± 5 V while consuming only 70 mA of idle current. The channel switching is performed via a serial digital control (which can accommodate "daisy chaining" of several devices) or via a parallel control allowing updating of an individual output without reprogramming the entire array. The AD8114/AD8115 is packaged in 100-lead LQFP package and is available over the extended industrial temperature range of 40°C to +85°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD8114/AD8115SPECIFICATIONS (V =
S
5 V, TA = +25 C, RL = 1 k
unless otherwise noted)
Parameter DYNAMIC PERFORMANCE 3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input-Output Input Voltage Noise DC PERFORMANCE Gain Error
Conditions 200 mV p-p, RL = 150 2 V p-p, RL = 150 0.1 dB, 200 mV p-p, RL = 150 0.1 dB, 2 V p-p, RL = 150 2 V p-p, RL = 150 0.1%, 2 V Step, RL = 150 2 V Step, RL = 150 NTSC or PAL, RL = 1 k NTSC or PAL, RL = 150 NTSC or PAL, RL = 1 k NTSC or PAL, RL = 150 f = 5 MHz f = 10 MHz f = 10 MHz, RL = 150 , One Channel 0.01 MHz to 50 MHz No Load RL = 1 k RL = 150 No Load, Channel-Channel RL = 1 k, Channel-Channel
Min
AD8114 /AD8115 Typ 225/200 100/125 25/40 20/40 5 40 375/450 0.05 0.05 0.05 0.05 70/64 60/52 90 16/18 0.05/0.2 0.05/0.2 0.2/0.35 0.01/0.5 0.01/0.5 0.75/1.5 0.2 10 5 1 ± 3.3 ±3 65 3 10 ± 3.5 5 10 2 60 50 20/30 70/80 27/30 70/80 27/30 16 ± 4.5 to ± 5.5 80 66 46 40 to +85 40
Max
Unit MHz MHz MHz MHz ns ns V/µs % % Degrees Degrees dB dB dB nV/Hz
150/125
0.08/0.6
Gain Matching Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range Voltage Range INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current
0.04/1
% % % % % ppm/° C M pF µA V V mA
DC, Enabled Disabled Disabled Disabled No Load IOUT = 20 mA Short Circuit Current Worst Case (All Configurations) Temperature Coefficient No Load Any Switch Configuration Per Output Selected
± 3.0 ± 2.5
15
± 3/± 1.5 1
5
mV µV/°C V pF M µA ns ns mV p-p mA mA mA mA mA V dB dB dB °C °C / W
50% UPDATE to 1% Settling
AVCC, Outputs Enabled, No Load AVCC, Outputs Disabled AVEE, Outputs Enabled, No Load AVEE, Outputs Disabled DVCC, Outputs Enabled, No Load DC f = 100 kHz f = 1 MHz Operating (Still Air) Operating (Still Air) 64
Supply Voltage Range PSRR
OPERATING TEMPERATURE RANGE Temperature Range JA
Specifications subject to change without notice.
2
REV. A
AD8114/AD8115 TIMING CHARACTERISTICS (Serial)
Parameter Serial Data Setup Time CLK Pulsewidth Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulsewidth CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 t7 Min 20 100 20 100 0 50 200 50 16 100 200 Limit Typ Max Unit ns ns ns ns ns ns ns ns µs ns ns
1 CLK 0 1 DATA IN 0 1 = LATCHED UPDATE 0 = TRANSPARENT
t2
t4
LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE OUT 7 (D3) OUT00 (D0)
t1
t3
OUT 7 (D4)
t5
TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL
t6
t7
DATA OUT
Figure 1. Timing Diagram, Serial Mode
Table I. Logic Levels
VIH RESET, SER/PAR CLK, DATA IN, CE, UPDATE 2.0 V min VIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE 0.8 V max VOH VOL IIH RESET, SER/PAR CLK, DATA IN, CE, UPDATE 20 µA max IIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE 400 µA min IOH IOL
DATA OUT 2.7 V min
DATA OUT 0.5 V max
DATA OUT 400 µA max
DATA OUT 3.0 mA min
REV. A
3
AD8114/AD8115 TIMING CHARACTERISTICS (Parallel)
Limit Parameter Data Setup Time CLK Pulsewidth Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulsewidth Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 Min 20 100 20 100 0 50 50 100 200 Max Unit ns ns ns ns ns ns ns ns ns
t2
1 CLK 0
t4
t1
D0D4 A0A2 1 0
t3
t5
1 = LATCHED UPDATE 0 = TRANSPARENT
t6
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
VIH RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE 2.0 V min VIL VOH VOL IIH RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE 20 µA max IIL RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE 400 µA min IOH IOL
RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE DATA OUT DATA OUT 0.8 V max 2.7 V min 0.5 V max
DATA OUT DATA OUT 400 µA max 3.0 mA min
4
REV. A
AD8114/AD8115
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Temperature Range Package Description Package Option
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V Internal Power Dissipation2 AD8114/AD8115 100-Lead Plastic LQFP (ST) . . . . 2.6 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . 65°C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air (T A = 25°C): 100-lead plastic LQFP (ST): JA = 40°C/W.
Model AD8114AST
40°C to +85°C 100-Lead Plastic ST-100 LQFP (14 mm × 14 mm) AD8114-EVAL Evaluation Board AD8115AST 40°C to +85°C 100-Lead Plastic ST-100 LQFP (14 mm × 14 mm) AD8115-EVAL Evaluation Board
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8114/AD8115 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
MAXIMUM POWER DISSIPATION
MAXIMUM POWER DISSIPATION W
5 TJ = 150 C 4
The maximum power that can be safely dissipated by the AD8114/AD8115 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8114/AD8115 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 3.
3
2
1
0 50 40 30 20 10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE C
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
REV. A
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