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Details, datasheet, quote on part number:AD8116-EB
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| Part: | AD8116-EB |
| Category: | Analog & Mixed-Signal Processing => Switches & Multiplexers => Analog Switches |
| Description: | 200 Mhz, 16 3 16 Buffered Video Crosspoint Switch |
| Company: | Analog Devices |
| Datasheet: | Download AD8116-EB datasheet File size : 811 kB |
| Request For quote: | Find where to buy AD8116-EB
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Datasheet text preview:
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FEATURES Large 16 16 High Speed Nonblocking Switch Array Switch Array Controllable via an 80-Bit Serial Word Serial Data Out Allows "Daisy Chaining" of Multiple AD8 116s to Create Large Switch Arrays Over 256 256 Complete Solution Buffered Inputs 16 Individual Output Amplifiers Drives 150 Loads Excellent Video Performance 60 MHz 0.1 dB Gain Flatness 0.01% Differential Gain Error (RL = 150 ) 0.01 Differential Phase Error (RL = 150 ) Excellent AC Performance 200 MHz 3 dB Bandwidth 300 V/ s Slew Rate Low Power of 900 mW (3.5 mW per Point) Low All Hostile Crosstalk of 70 dB @ 5 MHz Output Disable Allows Direct Connection of Multiple Device Outputs Chip Enable Allows Selection of Individual AD8116s in Large Arrays (or Parallel Programming of AD8116s) Reset Pin Allows Disabling of All Outputs (Connected Through a Capacitor to Ground Provides "PowerOn" Reset Capability) 128-Lead LQFP Package (14 mm 14 mm) APPLICATIONS Routing of High Speed Signals Including: Composite Video (NTSC, PAL, S, SECAM, etc.) Component Video (YUV, RGB, etc.) 3-Level Digital (HDB3) Video on Demand Ultrasound Communication Satellites PRODUCT DESCRIPTION
CLK DATA IN UPDATE CE
200 MHz, 16 16 Buffered Video Crosspoint Switch AD8116*
FUNCTIONAL BLOCK DIAGRAM
AD8116
CLK
80-BIT SHIFT REG. 80 PARALLEL LATCH 80 DECODE 5:16 DECODERS 256
SET INDIVIDUAL OR RESET ALL OUTPUTS TO "OFF"
DATA OUT UPDATE CE
RESET 16
RESET
16
OUTPUT BUFFER
+1 +1 +1 +1 +1
SWITCH MATRIX 16 INPUTS
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
ENABLE/DISABLE
16 OUTPUTS
4 RL = 50 3 2
0.5 0.4 0.3 0.2 200mV p-p 0.1 FLATNESS 2V p-p 0 0.1 2V p-p 0.2 200mV p-p 0.3 1G
1 0 1 2 3 4 100k
The AD8116 is a high speed 16 × 16 video crosspoint switch matrix. It offers a 3 dB signal bandwidth greater than 200 MHz and channel switch times of 60 ns with 0.1% settling. With 70 dB of crosstalk and 105 dB of isolation (@ 5 MHz), the AD8116 is useful in many high speed applications. The differential gain and differential phase errors of better than 0.01% and 0.01°, respectively, along with 0.1 dB flatness out to 60 MHz make the AD8116 ideal for video signal switching. The AD8116 includes output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off channels do not load the output bus. It operates on voltage
1M
10M FREQUENCY Hz
100M
Figure 1. Frequency Response
supplies of ± 5 V while consuming only 90 mA of idle current. The channel switching is performed via a serial digital control that can accommodate "daisy chaining" of several devices. The AD8116 is packaged in a 128-lead LQFP package occupying only 0.36 square inches, and is specified over the commercial temperature range of 0°C to 70°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
*Patent Pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
0.1dB FLATNESS dB
MAGNITUDE dB
AD8116SPECIFICATIONS (V =
S
5 V, TA = 25 C, RL = 1 k
unless otherwise noted.)
Min Limit Typ 200 120 80 300 60 25 20 60 45 0.01 0.01 0.01 0.01 70 60 105 15 0.995 0.999 0.992 0.999 1.000 1.000 0.15 0.5 45 Max Unit MHz MHz MHz V/µs ns MHz MHz MHz MHz % % Degrees Degrees dB dB dB nV/ Hz V/V V/V % % mV M pF µA V mA mA V pF M µA ns ns mV p-p mA mA mA mA mA mA V dB dB °C ° C/W Reference Figure 1 1 5 6 1 1 1 1 2 2 11 8 17 12 9 9 13 13 16 10 7 7
Parameter DYNAMIC PERFORMANCE 3 dB Bandwidth
Conditions 200 mV p-p, RL = 150 1 V p-p, RL = 150 2 V p-p, RL = 150 2 V Step, RL = 150 0.1%, 2 V Step, RL = 150 0.05 dB, 200 mV p-p, R L = 150 0.05 dB, 2 V p-p, RL = 150 0.1 dB, 200 mV p-p, RL = 150 0.1 dB, 2 V p-p, RL = 150 NTSC or PAL, R L = 1 k NTSC or PAL, R L = 150 NTSC or PAL, R L = 1 k NTSC or PAL, R L = 150 = 5 MHz = 10 MHz = 10 MHz, RL = 150 , One Channel 0.01 MHz to 50 MHz No Load RL = 1 k No Load, Ch-Ch RL = 1 k, Ch-Ch Worst-Case All Switch Configurations DC, Enabled Disabled Disabled
Slew Rate Settling Time Gain Flatness
NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input-Output Input Voltage Noise DC PERFORMANCE Gain Gain Matching OUTPUT CHARACTERISTICS Output Offset Voltage Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range Output Current Short Circuit Current INPUT CHARACTERISTICS Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time Switching Transient (Glitch) POWER SUPPLIES Supply Current
1
± 2.5 20
15 0.2 10 3 1 ±3 40 65 ±3 5 10 2 60 50 15
± 2.5 Any Switch Configuration 1
5
50% UPDATE to 1% Output Settling, 2 V Step
AVCC, Outputs Enabled, No Load AVCC, Outputs Disabled AVEE, Outputs Enabled, No Load AVEE, Outputs Disabled DVCC, Outputs Enabled, No Load DVEE, Outputs Enabled, No Load = 100 kHz = 1 MHz Operating (Still Air) Operating (Still Air)
Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range JA
Specifications subject to change without notice.
75 95 25 70 95 22.5 25 35 10 15 ± 4.5 to ± 5.5 60 40 0 to 70 37
2
REV. B
AD8116 TIMING CHARACTERISTICS
Parameter Data Setup Time CLK Pulsewidth Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulsewidth CLK to DATA OUT Valid Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz CLK, UPDATE Rise and Fall Times RESET Time
t2
1 CLK 0 1 DATA IN 0 1 = LATCHED UPDATE 0 = TRANSPARENT LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE
Symbol t1 t2 t3 t4 t5 t6 t7
t4
Min 20 100 20 100 0 50
Limit Typ
Max
Unit ns ns ns ns ns ns ns ns µs ns ns
200 50 16 100 200
t1
t3
OUT15 (D3)
OUT15 (D4)
OUT00 (D0)
t5
TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL
t6
t7
DATA OUT
0 1 2 3 4 5 6 7 8 9 10 CLOCK
15
20
25
75
79
DATA IN
DISABLE OUTPUT 13 ENABLE OUTPUT 15 ENABLE OUTPUT 14 ENABLE OUTPUT 12 ENABLE OUTPUT 11 DON'T CARE ENABLE OUTPUT 00 CONNECT TO INPUT 01 CONNECT TO NPUT 00 CONNECT TO INPUT 15 CONNECT TO INPUT 03 CONNECT TO INPUT 00
UPDATE
T=0
INCREASING TIME
Figure 2. Timing Diagram and Programming Example
Table I. Logic Levels
VIH
CLK, DATA IN, CE, UPDATE 2.0 V min
V IL
CLK, DATA IN, CE, UPDATE 0.8 V max
VOH
DATA OUT
VOL
DATA OUT
IIH
CLK, DATA IN, CE, UPDATE 20 µA max
IIL
CLK, DATA IN, CE, UPDATE 400 µA min
IOH
DATA OUT 400 µA max
IO L
DATA OUT
2.7 V min
0.5 V max
3.0 mA min
REV. B
3
AD8116
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V Internal Power Dissipation2 AD8116 128-Lead Plastic LQFP (ST) . . . . . . . . . . . . 3.5 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . 65°C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air (T A = 25°C): 128-lead plastic LQFP (ST): JA = 37°C/W.
The maximum power that can be safely dissipated by the AD8116 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8116 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 3.
5.0 TJ = 150 C 4.0
ORDERING GUIDE Model Temperature Range Package Description Package Option
MAXIMUM POWER DISSIPATION Watts
AD8116JST 0°C to 70°C AD8116-EB
128-Lead Plastic LQFP ST-128A (14 mm × 14 mm) Evaluation Board
3.0
2.0
1.0
0 50 40 30 20 10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE C
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8116 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. B
AD8116
Table II. Operation Truth Table Control Lines
CE 1 0
UPDATE X 1
CLK X f X
DATA IN X Data i X
DATA OUT X Data i-80 X
RESET 1 1
Operation/Comment No change in logic. The data on the DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 80 clocks later. Data in the serial shift register transfers into the parallel latches that control the switch array. Latches are transparent. Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged.
0
0
1
X
X
X
X
X
0
DATA IN
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DATA OUT
CLK CLK CE UPDATE LE OUTPUT CH CH BIT # SERIAL BIT #
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
D LE
D LE
D LE
D LE
D LE
D
LE
D LE
D LE
D LE
D LE
D LE
D
OUT0 0 LSB 79 Q
OUT0 OUT0 1 78 Q 2 77 Q
OUT0 OUT0 3 76 EN MSB 75 Q CLR Q
OUT1 0 74 Q
OUT14 OUT15 OUT15 OUT15 OUT15 OUT15 EN 5 CLR Q 0 LSB 4 Q 1 3 Q 2 2 Q 3 1 EN MSB 0 Q CLR Q
RESET
DECODE 256 16 SWITCH MATRIX
OUTPUT ENABLE
Figure 4. Logic Diagram
REV. B
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