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Details, datasheet, quote on part number:AD8555ACP-REEL
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| Part: | AD8555ACP-REEL |
| Category: | Analog & Mixed-Signal Processing => Amplifiers => PGA (Programmable Gain Amplifiers) |
| Description: | Zero-Drift, Single-Supply, Sensor Signal Amplifier With Digitally Programmable Gain And Offset.<<<>>>AD8555 is a Zero-drift Bridge Sensor Signal Amplifier With Digitally Programmable Gain And Output Offset. Designed to Easily And Accurately Convert Variable Pressure Sensor And Strain Bridge Outputs to a Well-defined Output Voltage Range, AD8555 Will Also Accurately Amplify Many Other Differential or Single Ended Sensor Outputs. AD8555 Utilizes Adi S Patented Low Noise Auto-zero And Digitrim Technologies to Create an Incredibly Accurate And Flexible Signal Processing Solution in a Very Compact Footprint. In Addition to Extremely Low Input Offset Voltage And Input Offset Voltage Drift And Very High DC And ac Cmrr, The AD8555 Also Includes a Pull-up Current Source at Each Analog Input to Allow Open Wire And Shorted Wire Fault Detection, And a Low-pass Filter Function Implemented Via a Single Low-cost External Capacitor. Output Clamping Set Via an External Reference Voltage Allows The AD8555 to Drive Lower Voltage ADCs Safely And Accurately.<<<>>>features <<<>>><<<>>>Very Low Offset Voltage:<<<>>>10 uv Max Over Temperature <<<>>>Very Low Input Offset Voltage Drift:<<<>>>50 NV/ C Max <<<>>>High CMRR: 96 DB <<<>>>Digitally Programmable Gain (span)<<<>>>and Output Offset Voltage |
| Company: | Analog Devices |
| Datasheet: | Download AD8555ACP-REEL datasheet File size : 516 kB |
| Request For quote: | Find where to buy AD8555ACP-REEL
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Datasheet text preview:
Zero-Drift, Digitally Programmable Sensor Signal Amplifier
AD8555
FEATURES
Very low offset voltage: 10 µV maximum over temperature Very low input offset voltage drift: 60 nV/°C maximum High CMRR: 96 dB minimum Digitally programmable gain and output offset voltage Single-wire serial interface Open and short wire fault detection Low-pass filtering Stable with any capacitive load Externally programmable output clamp voltage for driving low voltage ADCs LFCSP-16 and SOIC-8 packages 2.7 V to 5.5 V operation -40°C to +125°C operation
VDD VNEG A1 R4 R1 VSS P1 R3 VDD P2 R2 R5 VDD VSS DAC P4 VSS R7 FILT/ DIGOUT VSS A3 RF A4 P3 R6 VSS VDD VDD VOUT
FUNCTIONAL BLOCK DIAGRAM
VDD VCLAMP A5
A2 VPOS
APPLICATIONS
Automotive sensors Pressure and position sensors Thermocouple amplifiers Industrial weigh scales Precision current sensing Strain gages
VSS
Figure 1.
GENERAL DESCRIPTION
The AD8555 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the AD8555 also accurately amplifies many other differential or single-ended sensor outputs. The AD8555 uses the ADI patented low noise auto-zero and DigiTrim® technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint. Gain is digitally programmable in a wide range from 70 to 1,280 through a serial data interface. Gain adjustment can be fully simulated in-circuit and then permanently programmed with proven and reliable poly-fuse technology. Output offset voltage is also digitally programmable and is ratiometric to the supply voltage.
In addition to extremely low input offset voltage and input offset voltage drift and very high dc and ac CMRR, the AD8555 also includes a pull-up current source at the input pins and a pull-down current source at the VCLAMP pin. This allows open wire and shorted wire fault detection. A low-pass filter function is implemented via a single low cost external capacitor. Output clamping set via an external reference voltage allows the AD8555 to drive lower voltage ADCs safely and accurately. When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD and VSS. A lockout trim after gain and offset adjustment further ensures field reliability. The AD8555AR is fully specified over the extended industrial temperature range of -40°C to +125°C. Operating from single-supply voltages of 2.7 V to 5.5 V, the AD8555 is offered in the narrow 8-lead SOIC package and the 4 mm × 4 mm 16-lead LFCSP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
04598-0-001
AD8555 TABLE OF CONTENTS
Electrical Specifications .......... 3 Absolute Maximum Ratings... 7 Pin Configurations and Function Descriptions ... 8 Typical Performance Characteristics ............ 9 Theory of Operation .... 17 Gain Values.......... 18 Open Wire Fault Detection ....... 19 Shorted Wire Fault Detection ......... 19 Floating VPOS, VNEG, or VCLAMP Fault Detection.. 19 Device Programming........ 19 Filtering Function..... 25 Driving Capacitive Loads.......... 25 RF Interference ......... 26 Single-Supply Data Acquisition System .......... 26 Using the AD8555 with Capacitive Sensors ... 27 Outline Dimensions ..... 28 Ordering Guide ........ 28
REVISION HISTORY
4/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD8555 ELECTRICAL SPECIFICATIONS
At VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, -40°C TA +125°C, unless otherwise specified. Table 1.
Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Linearity Differential Gain Accuracy Differential Gain Temperature Coefficient RF RF Temperature Coefficient DAC Accuracy Ratiometricity Output Offset Temperature Coefficient VCLAMP Input Bias Current Input Voltage Range OUTPUT BUFFER STAGE Buffer Offset Short-Circuit Current Output Voltage, Low Output Voltage, High POWER SUPPLY Supply Current Power Supply Rejection Ratio DYNAMIC PERFORMANCE Gain Bandwidth Product Symbol VOS TCVOS IB IOS Conditions Min Typ 2 25 16 0.2 0.6 80 96 Max 10 65 22 25 1 1.5 3.8 Unit µV nV/°C nA nA nA nA V dB dB ppm ppm % % ppm/°C ppm/°C k ppm/°C % ppm mV ppm FS/°C nA nA V mV mA mV V mA dB MHz MHz MHz V/µs µs nV/Hz µV p-p dB
TA = 25°C TA = 25°C
12
CMRR
VCM = 0.9 V to 3.6 V, AV = 70 VCM = 0.9 V to 3.6 V, AV = 1,280 VO = 0.2 V to 3.4 V VO = 0.2 V to 4.8 V Second Stage Gain = 17.5 to 100 Second Stage Gain = 140 to 200 Second Stage Gain = 17.5 to 100 Second Stage Gain = 140 to 200
92 112 20 1000 0.35 0.5 15 40 18 700 0.7 50 5 3.3 200 500
1.6 2.5 40 100 22
14
AV = 70, Offset Codes = 8 to 248 AV = 70, Offset Codes = 8 to 248 AV = 70, Offset Codes = 8 to 248
0.8 35 15
TA = 25°C, VCLAMP = 5 V 1.25
4.94 7 15 10 30
ISC VOL VOH ISY PSRR GBP
5 RL = 10 k to 5 V RL = 10 k to 0 V VO = 2.5 V, VPOS = VNEG = 2.5V, VDAC Code = 128 AV = 70 First Gain Stage, TA = 25°C Second Gain Stage, TA = 25°C Output Buffer Stage AV = 70, RL = 10 k, C L = 100 pF To 0.1%, AV = 70, 4 V Output Step TA = 25°C, f = 1 kHz f = 0.1 Hz to 10 Hz VIN = 16.75 mV rms, f = 1 kHz, AV = 100 4.94 2.0 109 125 2 8 1.5 1.2 8 32 0.5 -100
2.5
Output Buffer Slew Rate Settling Time NOISE PERFORMANCE Input Referred Noise Low Frequency Noise Total Harmonic Distortion
SR ts
en p-p THD
Rev. 0 | Page 3 of 28
AD8555
Parameter DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time between Pulses at DIGIN DIGIN Low DIGIN High DIGOUT Logic 0 DIGOUT Logic 1 Symbol Conditions Min Typ 2 tw0 tw1 tws TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C 0.05 50 10 4 1 4 10 Max Unit µA µs µs µs V V V V
1
Rev. 0 | Page 4 of 28
AD8555
At VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VO = 1.35 V, -40°C TA +125°C, unless otherwise specified. Table 2.
Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Linearity Differential Gain Accuracy Differential Gain Temperature Coefficient RF RF Temperature Coefficient DAC Accuracy Ratiometricity Output Offset Temperature Coefficient VCLAMP Input Bias Current Input Voltage Range OUTPUT BUFFER STAGE Buffer Offset Short-Circuit Current Output Voltage, Low Output Voltage, High POWER SUPPLY Supply Current Power Supply Rejection Ratio DYNAMIC PERFORMANCE Gain Bandwidth Product Symbol VOS TCVOS IB IOS Conditions Min Typ 2 25 16 0.2 Max 10 60 1 1.5 1.6 Unit µV nV/°C nA nA nA V dB dB ppm ppm % % ppm/°C ppm/°C 22 k ppm/°C % ppm mV ppm FS/°C nA nA V mV mA mV V mA dB MHz MHz MHz V/µs µs nV/Hz µV p-p dB
TA = 25°C TA = 25°C
12
CMRR
VCM = 0.9 V to 1.3 V, AV = 70 VCM = 0.9 V to 1.3 V, AV = 1,280 VO = 0.2 V to 3.4 V VO = 0.2 V to 4.8 V Second Stage Gain = 17.5 to 100 Second Stage Gain = 140 to 200 Second Stage Gain = 17.5 to 100 Second Stage Gain = 140 to 200
0.5 80 96
92 112 20 1000 0.35 0.5 15 40 18 700 0.7 50 5 3.3 200 500
14
AV = 70, Offset Codes = 8 to 248 AV = 70, Offset Codes = 8 to 248 AV = 70, Offset Codes = 8 to 248
35
TA = 25°C, VCLAMP = 2.7 V 1.25
2.64 7 15 9.5 30
ISC VOL VOH ISY PSRR GBP
4.5 RL = 10 k to 5 V RL = 10 k to 0 V VO = 1.35 V, VPOS = VNEG = 1.35 V, VDAC Code = 128 AV = 70 First Gain Stage, TA = 25°C Second Gain Stage, TA = 25°C Output Buffer Stage AV = 70, RL = 10 k, CL = 100 pF To 0.1%, AV = 70, 4 V Output Step TA = 25°C, f = 1 kHz f = 0.1 Hz to 10 Hz VIN = 16.75 mV rms, f = 1 kHz, AV = 100 2.64 2.0 109 125 2 8 1.5 1.2 8 32 0.3 -100
Output Buffer Slew Rate Settling Time NOISE PERFORMANCE Input Referred Noise Low Frequency Noise Total Harmonic Distortion
SR ts
en p-p THD
Rev. 0 | Page 5 of 28
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