Details, datasheet, quote on part number: AD9002A
CategoryData Conversion => ADC (Analog to Digital Converters)
DescriptionHigh Speed 8-Bit Monolithic A/D Converter
CompanyAnalog Devices
DatasheetDownload AD9002A datasheet
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Features, Applications

FEATURES 150 MSPS Encode Rate Low Input Capacitance: 17 pF Low Power: 5.2 V Single Supply MIL-STD-883 Compliant Versions Available APPLICATIONS Radar Systems Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal Intelligence

The an 8-bit, high-speed, analog-to-digital converter. The AD9002 is fabricated in an advanced bipolar process that allows operation at sampling rates in excess of 150 megasamples/ second. Functionally, the AD9002 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ECL compatible output latches. An exceptionally wide large signal analog input bandwidth of 160 MHz is due to an innovative comparator design and very close attention to device layout considerations. The wide input bandwidth of the AD9002 allows very accurate acquisition of high speed pulse inputs, without an external track-and-hold. The comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. The AD9002 provides an external hysteresis control pin that can be used to optimize comparator sensitivity to further improve performance. Additionally, the AD9002's low power dissipation 750 mW makes it usable over the full extended temperature range. The AD9002 also incorporates an overflow bit to indicate overrange inputs. This overflow output can be disabled with the overflow inhibit pin.

The AD9002 is available in two grades, one with 0.5 LSB linearity and one with 0.75 LSB linearity. Both versions are offered in an industrial grade, to +85C, packaged a 28-lead DIP and a 28-leaded JLCC. The military temperature range devices, to +125C, are available in ceramic DIP and LCC packages and comply with MIL-STD-883 Class B.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 Analog Devices, Inc., 2001

ELECTRICAL CHARACTERISTICS (V 5.2 V; Differential Reference Voltage 2.0 V; unless otherwise noted)

Parameter RESOLUTION DC ACCURACY Differential Linearity Integral Linearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Bias Current1 Input Resistance Input Capacitance Large Signal Bandwidth2 Input Slew Rate3 REFERENCE INPUT Reference Ladder Resistance Ladder Temperature Coefficient Reference Input Bandwidth DYNAMIC PERFORMANCE Conversion Rate Aperture Delay Aperture Uncertainty (Jitter) Output Delay (tPD)4, 5 Transient Response6 Overvoltage Recovery Time7 Output Rise Time4 Output Fall Time4 Output Time Skew4, 8 ENCODE INPUT Logic "1" Voltage4 Logic "0" Voltage4 Logic "1" Current Logic "0" Current Input Capacitance Encode Pulsewidth (Low)9 Encode Pulsewidth (High)9 OVERFLOW INHIBIT INPUT 0 V Input Current AC LINEARITY10 Effective Bits11 In-Band Harmonics to 1.23 MHz to 9.3 MHz to 19.3 MHz Signal-to-Noise Ratio12 Two Tone Intermod Rejection13 DIGITAL OUTPUTS4 Logic "1" Voltage Logic "0" Voltage POWER SUPPLY14 Supply Current (5.2 V) Nominal Power Dissipation Reference Ladder Dissipation Power Supply Rejection Ratio15

25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C

NOTES 1 Measured with AIN V. 2 Measured by FFT analysis where fundamental is 3 dBc. 3 Input slew rate derived from rise time 90%) of full scale input. 4 0utputs terminated through V. 5 Measured from ENCODE in to data out for LSB only. 6 For full-scale step input, 8-bit accuracy is attained in specified time. 7 Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage. 8 Output time skew includes high-to-low and low-to-high transitions as well as

bit-to-bit time skew differences. 9 ENCODE signal rise/fall times should be less than 10 ns for normal operation. 10 Measured at 125 MSPS encode rate. 11 Analog input frequency = 1.23 MHz. 12 RMS signal to rms noise, with 1.23 MHz analog input signal. 13 Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz. 14 Supplies should remain stable within 5% for normal operation. 15 Measured 5%. Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS 1 Recommended Operating Conditions

Supply Voltage (VS). 6 V Analog-to-Digital Supply Voltage Differential. 0.5 V Analog Input Voltage. VS +0.5 V Digital Input Voltage. VS 0 V Reference Input Voltage (+VREF +0.1 V Differential Reference Voltage. 2.1 V Reference Midpoint Current. 4 mA ENCODE to ENCODE Differential Voltage. 4 V Digital Output Current. 20 mA Operating Temperature Range to +125C Storage Temperature Range. to +150C Junction Temperature3. 150C Lead Soldering Temperature (10 sec). 300C

NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 +VREF VREF under all circumstances. 3 Maximum junction temperature (t J max) should not exceed 175 C for ceramic packages, and 150 C for plastic packages: = PD (JA) tA PD (JC) + tC where PD = power dissipation JA = thermal impedance from junction to ambient ( C/W) JC = thermal impedance from junction to case ( C/W) tA = ambient temperature ( C) tC = case temperature ( C) Typical thermal impedances are: Ceramic DIP = 20C/W Ceramic LCC = 23C/W PLCC = 19C/W.

Input Voltage Parameter VS +VREF VREF Analog Input Min 5.46 VREF 2.1 VREF Nominal V 2.0 Max 4.94 +0.1 +VREF

100% production tested. 100% production tested at 25C, and sample tested at specified temperatures. Test Level III Sample tested only. Test Level IV Parameter is guaranteed by design and characterization testing. Test Level V Parameter is a typical value only. Test Level VI All devices are 100% production tested 25C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.

*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip Carrier, J-Formed Leads.

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9002 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.


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