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Details, datasheet, quote on part number:AD9002T
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Datasheet text preview:
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FEATURES 150 MSPS Encode Rate Low Input Capacitance: 17 pF Low Power: 750 mW 5.2 V Single Supply MIL-STD-883 Compliant Versions Available APPLICATIONS Radar Systems Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal Intelligence
High-Speed 8-Bit Monolithic A/D Converter AD9002
FUNCTIONAL BLOCK DIAGRAM
OVERFLOW INHIBIT ANALOG IN R +VREF R
255 256
AD9002
OVERFLOW BIT 8 (MSB) D E C O D I N G L O G I C
BIT 7 BIT 6 BIT 5
R
128
R/2 REFMID R/2
127
L A T C H
BIT 4 BIT 3
R
GENERAL DESCRIPTION
2
BIT 2 BIT 1 (LSB)
The AD9002 is an 8-bit, high-speed, analog-to-digital converter. The AD9002 is fabricated in an advanced bipolar process that allows operation at sampling rates in excess of 150 megasamples/ second. Functionally, the AD9002 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ECL compatible output latches. An exceptionally wide large signal analog input bandwidth of 160 MHz is due to an innovative comparator design and very close attention to device layout considerations. The wide input bandwidth of the AD9002 allows very accurate acquisition of high speed pulse inputs, without an external track-and-hold. The comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. The AD9002 provides an external hysteresis control pin that can be used to optimize comparator sensitivity to further improve performance. Additionally, the AD9002's low power dissipation of 750 mW makes it usable over the full extended temperature range. The AD9002 also incorporates an overflow bit to indicate overrange inputs. This overflow output can be disabled with the overflow inhibit pin.
R VREF ENCODE ENCODE GND HYSTERESIS VS
1
The AD9002 is available in two grades, one with 0.5 LSB linearity and one with 0.75 LSB linearity. Both versions are offered in an industrial grade, 25°C to +85°C, packaged in a 28-lead DIP and a 28-leaded JLCC. The military temperature range devices, 55°C to +125°C, are available in ceramic DIP and LCC packages and comply with MIL-STD-883 Class B.
REV. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9002SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V = 5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
S
Parameter RESOLUTION DC ACCURACY Differential Linearity Integral Linearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Bias Current1 Input Resistance Input Capacitance Large Signal Bandwidth2 Input Slew Rate3 REFERENCE INPUT Reference Ladder Resistance Ladder Temperature Coefficient Reference Input Bandwidth DYNAMIC PERFORMANCE Conversion Rate Aperture Delay Aperture Uncertainty (Jitter) Output Delay (tPD)4, 5 Transient Response6 Overvoltage Recovery Time7 Output Rise Time4 Output Fall Time4 Output Time Skew4, 8 ENCODE INPUT Logic "1" Voltage4 Logic "0" Voltage4 Logic "1" Current Logic "0" Current Input Capacitance Encode Pulsewidth (Low)9 Encode Pulsewidth (High)9 OVERFLOW INHIBIT INPUT 0 V Input Current AC LINEARITY10 Effective Bits11 In-Band Harmonics dc to 1.23 MHz dc to 9.3 MHz dc to 19.3 MHz Signal-to-Noise Ratio12 Two Tone Intermod Rejection13 DIGITAL OUTPUTS4 Logic "1" Voltage Logic "0" Voltage POWER SUPPLY14 Supply Current (5.2 V) Nominal Power Dissipation Reference Ladder Dissipation Power Supply Rejection Ratio15
Temp
AD9002AD/AJ Min Typ Max 8
AD9002BD/BJ Min Typ Max 8
AD9002SD/SE Min Typ Max 8
AD9002TD/TE Min Typ Max 8
Unit Bits
2 5 °C Full 2 5 °C Full Full 2 5 °C Full 2 5 °C Full Full 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full Full Full 2 5 °C 2 5 °C 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C
0.75 1.0 0.6 1.0 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 1.1 1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 14 17 10 12
0.6
0.5 0.75 0.4 0.5 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 1.1 1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 14 17 10 12
0.4
0.75 1.0 0.6 1.0 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 1.1 1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 14 17 10 12
0.6
0.5 0.75 0.4 0.5 1.2 GUARANTEED 8 4 20 60 25 200 17 160 440 80 0.25 10 150 1.3 15 3.7 6 6 0.6 1.1 1.5 150 120 3 1.5 1.5 144 7.6 48 46 55 50 44 47.6 60 300 200 200 22 14 17 10 12
0.4
LSB LSB LSB LSB
mV mV mV mV µV/°C µA µA k pF MHz V/µs / ° C MHz MSPS ns ps ns ns ns ns ns ns V V µA µA pF ns ns µA Bits dB dB dB dB dB V V mA mA mW mW mV/V
22
22
22
40
110
40
110
40
110
40
110
125 2.5
125 5.5 3.0 2.5 2.5
125 5.5 3.0 2.5 2.5
125 5.5 3.0 2.5 2.5
5.5 3.0 2.5
1.1 1.5 145 750 50 0.8 175 200 1.5
1.1 1.5 145 750 50 0.8 175 200 1.5
1.1 1.5 145 750 50 0.8 175 200 1.5
1.1 1.5 145 750 50 0.8 175 200 1.5
NOTES 1 Measured with AIN = 0 V. 2 Measured by FFT analysis where fundamental is 3 dBc. 3 Input slew rate derived from rise time (10 to 90%) of full scale input. 4 0utputs terminated through 100 to 2 V. 5 Measured from ENCODE in to data out for LSB only. 6 For full-scale step input, 8-bit accuracy is attained in specified time. 7 Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage. 8 Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences. 9 ENCODE signal rise/fall times should be less than 10 ns for normal operation. 10 Measured at 125 MSPS encode rate. 11 Analog input frequency = 1.23 MHz. 12 RMS signal to rms noise, with 1.23 MHz analog input signal. 13 Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz. 14 Supplies should remain stable within ± 5% for normal operation. 15 Measured at 5.2 V ± 5%. Specifications subject to change without notice.
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AD9002
ABSOLUTE MAXIMUM RATINGS 1 Recommended Operating Conditions
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Analog-to-Digital Supply Voltage Differential . . . . . . . . 0.5 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . VS to +0.5 V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . VS to 0 V Reference Input Voltage (+VREF VREF)2 . . . 3.5 V to +0.1 V Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ± 4 mA ENCODE to ENCODE Differential Voltage . . . . . . . . . . . 4 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature Range AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . 25°C to +85°C AD9002SE/SD/TD/TE . . . . . . . . . . . . . . 55°C to +125°C Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300°C
NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 +VREF VREF under all circumstances. 3 Maximum junction temperature (t J max) should not exceed 175°C for ceramic packages, and 150°C for plastic packages: tJ = PD (JA) + tA PD (JC) + tC where PD = power dissipation JA = thermal impedance from junction to ambient (°C/W) JC = thermal impedance from junction to case (°C/W) tA = ambient temperature (°C) tC = case temperature (°C) Typical thermal impedances are: Ceramic DIP JA = 56°C/W; JC = 20°C/W Ceramic LCC JA = 69°C/W; JC = 23°C/W PLCC JA = 60°C/W; JC = 19°C/W.
Input Voltage Parameter VS +VREF VR E F Analog Input Min 5.46 VR E F 2.1 VR E F Nominal 5.20 0.0 V 2.0 Max 4.94 +0.1 +VREF +VREF
EXPLANATION OF TEST LEVELS
Test Level I Test Level II
100% production tested. 100% production tested at 25°C, and sample tested at specified temperatures. Test Level III Sample tested only. Test Level IV Parameter is guaranteed by design and characterization testing. Test Level V Parameter is a typical value only. Test Level VI All devices are 100% production tested at 25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
ORDERING GUIDE
Model AD9002AD AD9002BD AD9002AJ AD9002BJ AD9002SD/883B AD9002SE/883B AD9002TD/883B AD9002TE/883B
Package Linearity Temperature Range Option* 0.75 LSB 0.50 LSB 0.75 LSB 0.50 LSB 0.75 LSB 0.75 LSB 0.50 LSB 0.50 LSB 25°C to +85°C 25°C to +85°C 25°C to +85°C 25°C to +85°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C D-28 D-28 J-28 J-28 D-28 E-28A D-28 E-28A
*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip Carrier, J-Formed Leads.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9002 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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3
AD9002
FUNCTIONAL DESCRIPTION Pin # 1 2 Mnemonic DIGITAL GROUND OVERFLOW INH Description One of four digital ground pins. All digital ground pins should be connected together. OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs. Overflow Enabled (Floating or 5.2 V) of D1D8 10 0 0 0 0 0 0 0 0XXXXX XXX
Analog Input VIN > +VREF VIN +VREF 3 4 5 6 7 8 9 10 11 12 13 14 15 1619 20 21, 22 23 24, 25 26 27 HYSTERESIS + V REF ANALOG INPUT ANALOG GROUND ENCODE ENCODE ANALOG GROUND ANALOG INPUT VREF R E F MID DIGITAL GROUND DIGITAL VS D1 (LSB) D2D5 DIGITAL GROUND ANALOG VS DIGITAL GROUND D6, D7 D8 (MSB) OVERFLOW
Overflow Inhibited (GND) of D1D8 01 1 1 1 1 1 11
0XXXX XX XX
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change from 5.2 V to 2.2 V at the Hysteresis control pin. Normally converted to 5.2 V. The most positive reference voltage for the internal resistor ladder. One of two analog input pins. Both analog input pins should be connected together. One of two analog ground pins. Both analog ground pins should be connected together. Noninverted input of the differential encode input. This pin is driven in conjunction with ENCODE. Data is latched on the rising edge of the ENCODE signal. Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE. One of two analog ground pins. Both analog ground pins should be connected together. One of two analog input pins. Both analog inputs should be connected together. The most negative reference voltage for the internal resistor ladder. The midpoint tap on the internal resistor ladder. One of four digital ground pins. All digital ground pins should be connected together. One of two negative digital supply pins (nominally 5.2 V). Both digital supply pins should be connected together. Digital Data Output Digital Data Output One of four digital ground pins. All digital ground pins should be connected together. One of two negative analog supply pins (nominally 5.2 V). Both analog supply pins should be connected together One of four digital ground pins. All digital ground pins should be connected together. Digital Data Output Digital Data Output Overflow data output. Logic high indicates an input overvoltage (V IN > +VREF) if OVERFLOW INHIBIT is enabled (overflow enabled, 5.2 V). See OVERFLOW INHIBIT.
28
DIGITAL VS
One of two negative digital supply pins (nominally 5.2 V). Both digital supply pins should be connected together.
PIN DESIGNATIONS
DIP
DIGITAL 1 GROUND OVERFLOW INH 2 HYSTERESIS 3 +VREF
4 28 DIGITAL VS 27 OVERFLOW
LCC
DIGITAL GROUND DIGITAL VS OVERFLOW D8(MSB) HYSTERESIS OVERFLOW INH
JLCC
DIGITAL GROUND ANALOG VS DIGITAL GROUND
D7 D6
ANALOG INPUT 5 ANALOG 6 GROUND ENCODE 7
24 D6 23 DIGITAL
4
3
2
1 28 27 26
25 24 23 22 21 20 19
D5
18 17
25 D7
+VREF
26 D8(MSB)
ANALOG VS
AD9002
TOP VIEW ENCODE 8 (Not to Scale) 21 ANALOG VS ANALOG 9 20 DIGITAL GROUND GROUND 19 D5 ANALOG INPUT 10 VREF 11 REFMID 12 DIGITAL 13 GROUND DIGITAL VS 14
18 D4 17 D3 16 D2 15 D1(LSB)
GROUND 22 ANALOG VS
ANALOG INPUT 5 ANALOG GROUND 6 ENCODE 7 ENCODE 8 ANALOG 9 GROUND ANALOG INPUT 10 VREF 11
25 24
AD9002
TOP VIEW (Not to Scale)
23 22 21 20 19
D7 D6 DIGITAL GROUND ANALOG VS ANALOG VS DIGITAL GROUND D5
D8(MSB) OVERFLOW DIGITAL VS DIGITAL GROUND OVERFLOW INH HYSTERESIS +VREF
26 27 28 1 2 3 4 5 6 7 8 9 10 11
D4 D3 D2 D1(LSB) DIGITAL VS DIGITAL GROUND REFMID
AD9002
TOP VIEW
(Not to Scale)
16 15 14 13 12
DIGITAL GROUND DIGITAL VS
4
ENCODE ANALOG GROUND ANALOG INPUT VREF
ANALOG GROUND
ANALOG INPUT
ENCODE
12 13 14 15 16 17 18
REFMID
D1(LSB) D2 D3
D4
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AD9002
N+1 ANALOG INPUT N APERTURE DELAY ENCODE N+2
t PD
OUTPUT DATA N1 N N+1
Figure 1. Timing Diagram
AD9002
AD9002
+VREF R
AD9002
R/2 ENCODE ENCODE ANALOG INPUT 5.2V 5.2V R/2 DIGITAL OUTPUT R VREF REFMID
5.2V
5.2V
5.2V COMPARATOR CELLS
Figure 2. Input/Output Circuits
OVERFLOW INHIBIT HYSTERESIS DIGITAL GROUND
.1 F 5.2V AVS OVERFLOW HYSTERESIS 00 AD1 AD2 AD3 2V 0.1 F 1k 1 1k E F OV0 RFLOW INH ANALOG IN ENCODE ENCODE VREF D8 D7 D6 D5 D4
DIGITAL VS OVERFLOW D8 (MSB)
+VREF
k 1k 1k 1k 1k 1k 1k 1k 1k 1
ANALOG INPUT ANALOG GROUND ENCODE ENCODE ANALOG GROUND ANALOG INPUT
D7 D6 DIGITAL GROUND ANALOG VS DIGITAL GROUND
D9002
+VREF GROUND
D3 D2 D1
D5 D4
STATIC BURN IN AD1 = 0V AD2 = ECL HIGH DYNAMIC BURN IN AD1
AD3 = ECL LOW 0V 2V ECL HIGH ECL LOW ECL HIGH
VREF
D1 (LSB) DIGITAL GROUND DIGITAL REFMID VS
D2
D3
AD2
Figure 4. Die Layout and Mechanical Information
AD3 A ALL RESISTORS 5%, LL CAPACITORS 20%, ALL SUPPLIES 5%
ECL LOW F
igure 3. Burn-in Diagram
Die Dimensions . . . . . . . . . . . . . . . . . 106 × 114 × 15 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic) Bond Wire . . . . . . . . . . . . . 1-1.3 mil Gold; Gold Ball Bonding 5
REV. F
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