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Details, datasheet, quote on part number:AD9012TE
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Datasheet text preview:
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FEATURES 100 MSPS Encode Rate Very Low Input Capacitance--16 pF Low Power--1 W TTL Compatible Outputs MIL-STD-883 Compliant Versions Available APPLICATIONS Radar Guidance Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal Intelligence
OVERFLOW INHIBIT ANALOG IN VREF R R
High-Speed 8-Bit TTL A/D Converter AD9012
FUNCTIONAL BLOCK DIAGRAM
AD9012
256
OVERFLOW
255
D8 (MSB) D E C O D I N G L O G I C D7 D6 D5 D4 D3 D2 D1 (LSB)
R
128
R/2 REFMID R/2
127
L A T C H
R
GENERAL DESCRIPTION
2
The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital converter. The AD9012 is fabricated in an advanced bipolar process that allows operation at sampling rates up to one hundred megasamples/second. Functionally, the AD9012 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the TTL compatible output latches. The exceptionally wide large-signal analog input bandwidth of 160 MHz is due to an innovative comparator design and very close attention to device layout considerations. The wide input bandwidth of the AD9012 allows very accurate acquisition of high speed pulse inputs without an external track-and-hold. The comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. The AD9012 is available in two grades: one with 0.5 LSB linearity and one with 0.75 LSB linearity. Both versions are
R VREF ENCODE VS VS
1
GND
HYSTERESIS
offered in an industrial grade, 25°C to +85°C, packaged in a 28-lead DIP and a 28-lead JLCC. The military temperature range devices, 55°C to +125°C, are available in ceramic DIP and LCC packages and are compliant to MIL-STD-883 Class B. The AD9012 is available in versions compliant with MIL-STD883. Refer to the Analog Devices Military Products Databook or current AD9012/883B data sheet for detailed specifications.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9012SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter RESOLUTION DC ACCURACY Differential Linearity Integral Linearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Bias Current1 Input Resistance Input Capacitance Large Signal Bandwidth2 Analog Input Slew Rate3 REFERENCE INPUT Reference Ladder Resistance Ladder Temperature Coefficient Reference Input Bandwidth DYNAMIC PERFORMANCE Conversion Rate Aperture Delay Aperture Uncertainty (Jitter) Output Delay (tPD)4, 5 Transient Response6 Overvoltage Recovery Time7 Output Rise Time4 Output Fall Time4 Output Time Skew4, 8 ENCODE INPUT Logic "1" Voltage4 Logic "0" Voltage4 Logic "1" Current Logic "0" Current Input Capacitance Encode Pulsewidth (Low)9 Encode Pulsewidth (High)9 OVERFLOW INHIBIT INPUT 0 V Input Current AC LINEARITY10 Effective Bits11 In-Band Harmonics dc to 1.23 MHz dc to 9.3 MHz dc to 19.3 MHz Signal-to-Noise Ratio12 Noise Power Ratio13 DIGITAL OUTPUT Logic "1" Voltage Logic "0" Voltage 2 5 °C Full 2 5 °C Full Full 2 5 °C Full 2 5 °C Full Full 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full Full Full 2 5 °C 2 5 °C 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full I VI I VI VI I VI I VI V I VI I III V V VI V V I V V I V V I I V VI VI VI VI V I I VI V I V V I V VI VI I VI I VI V V I 48 46 Temp 8 0.75 1.0 0.6 1.0 1.2 GUARANTEED 7 6 25 60 25 200 16 160 440 80 0.25 10 100 3.8 15 4.9 8 8 6.6 3.3 3.0 200 200 25 18 15 18 10 13 0.6
(+VS = +5.0 V; VS = 5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted.)
AD9012BQ/BJ M in Typ M ax 8 0.5 0.75 0.4 0.5 1.2 GUARANTEED 7 6 25 60 200 16 160 440 80 0.25 10 100 3.8 15 4.9 8 8 6.6 3.3 3.0 200 200 25 18 15 18 10 13 0.4 AD9012SQ/SE Min Typ Max 8 0.75 1.0 0.6 1.0 1.2 GUARANTEED 7 6 25 60 200 16 160 440 80 0.25 10 100 3.8 15 4.9 8 8 6.6 3.3 3.0 200 200 25 18 15 18 10 13 0.6 AD9012TQ/TE M in Typ Max 8 0.5 0.75 0.4 0.5 1.2 GUARANTEED 7 6 25 60 200 16 160 440 80 0.25 10 100 3.8 15 4.9 8 8 6.6 3.3 3.0 200 200 18 15 18 10 13 0.4 Unit Bits LSB LSB LSB LSB
Test AD9012AQ/AJ Level Min Typ Max
mV mV mV mV µV/°C µA µA k pF MHz V/µs / ° C MHz MSPS ns ps ns ns ns ns ns ns V V µA µA pF ns ns µA Bits dBc dBc dBc dBc dBc V V mA mA mA mA mW mW mV/V
40
110
40
110
40
110
40
110
75 4
75 11 8.0 4.3 4
75 11 8.0 4.3 4
75 11 8.0 4.3 4
11 8.0 4.3
2.0 0.8 250 400 2.5 2.5 2.5 200 7.5 55 50 44 47.6 37 250
2.0 0.8 250 400 2.5 2.5 2.5 200 7.5 48 46 55 50 44 47.6 37 250
2.0 0.8 250 400 2.5 2.5 2.5 200 7.5 48 46 55 50 44 47.6 37 250
2.0 0.8 250 400 2.5 2.5 2.5 200 7.5 48 46 55 50 44 47.6 37 250
2.4 0.4 33 152 955 44 0.85 45 48 179 191 2.5
2.4 0.4 33 152 955 44 0.85 45 48 179 191 2.5
2.4 0.4 33 152 955 44 0.8 45 48 179 191 2.5
2.4 0.4 33 152 955 44 0.8 45 48 179 191 2.5
POWER SUPPLY14 Positive Supply Current (+5.0 V) 25°C Full Supply Current (5.2 V) 2 5 °C Full Nominal Power Dissipation 2 5 °C Reference Ladder Dissipation 2 5 °C 15 Power Supply Rejection Ratio 2 5 °C
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AD9012
NOTES 1 Measured with Analog Input = 0 V. 2 Measured by FFT analysis where fundamental is 3 dBc. 3 Input slew rate derived from rise time (10% to 90%) of full-scale step input. 4 Outputs terminated with two equivalent 'LS00 type loads. (See load circuit.) 5 Measured from ENCODE into data out for LSB only. 6 For full-scale step input, 8-bit accuracy is attained in specified time. 7 Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage. 8 Output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences.
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ENCODE signal rise/fall times should be less than 30 ns for normal operation. Measured at 75 MSPS encode rate. Harmonic data based on worst case harmonics. 11 Analog input frequency = 1.23 MHz. 12 RMS signal to rms noise, including harmonics with 1.23 MHz. analog input signal. 13 NPR measured @ 0.5 MHz. Noise Source is 250 mW (rms) from 0.5 MHz to 8 MHz. 14 Supplies should remain stable within ± 5% for normal operation. 15 Measured at 5.2 V ± 5% and +5.0 V ± 5%. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS 1
VS F TTL OUTPUT 15pF 1k
Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . . 6 V Analog to Digital Supply Voltage Differential (VS) . . . 0.5 V Negative Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . 6 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . VS to +0.5 V ENCODE Input Voltage . . . . . . . . . . . . . . . . . 0.5 V to +5 V OVERFLOW INH Input Voltage . . . . . . . . . . . 5.2 V to 0 V Reference Input Voltage (+VREF VREF)2 . . . 3.5 V to +0.1 V Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ± 4 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . . . . . 25°C to +85°C AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . 55°C to +125°C Storage Temperature Range . . . . . . . . . . . 65°C to +150°C Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300°C
NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 +VREF VREF under all circumstances. 3 Maximum junction temperature (t J max) should not exceed 150°C for ceramic and plastic packages: tJ = PD (JA) + tA PD (JC) + tc where PD = power dissipation JA = thermal impedance from junction to ambient (°C/W) JC = thermal impedance from junction to case (°C/W) tA = ambient temperature (°C) tC = case temperature (°C) typical thermal impedances are: Ceramic DIP JA = 42°C/W; JC = 10°C/W Ceramic LCC JA = 50°C/W; JC = 15°C/W JLCC JA = 59°C/W; JC = 15°C/W.
igure 1. Load Circuit
EXPLANATION OF TEST LEVELS Test Level
I
100% production tested.
II 100% production tested at 25°C, and sample tested at specified temperatures. AC testing done on sample basis. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI All devices are 100% production tested at 25°C. 100% production tested at temperature extremes for extended temperature devices; guaranteed by design and characterization testing for industrial devices.
ORDERING GUIDE
Device AD9012AQ AD9012BQ AD9012AJ AD9012BJ AD9012SQ AD9012SE AD9012TQ AD9012TE
Linearity 0.75 LSB 0.50 LSB 0.75 LSB 0.50 LSB 0.75 LSB 0.75 LSB 0.50 LSB 0.50 LSB
Temperature Ranges 25°C to +85°C 25°C to +85°C 25°C to +85°C 25°C to +85°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C
Package Options* Q-28 Q-28 J-28A J-28A Q-28 E-28A Q-28 E-28A
Recommended Operating Conditions
Parameter VS + VS +VREF VR E F Analog Input
Min 5.46 +4.75 VR E F 2.1 VR E F
Input Voltage Nominal 5.20 5.00 0.0 V 2.0
Max 4.94 +5.25 +0.1 + V REF + V REF
*E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier; Q = Cerdip.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9012 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9012
PIN FUNCTION DESCRIPTIONS
Pin # 11 12
Name DIGITAL +VS OVERFLOW INH
Description One of three positive digital supply pins (nominally +5.0 V). OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN + VREF).
ANALOG INPUT V IN + V REF V IN < + V REF OVERFLOW ENABLED (FLOATING) OF Dl D2 D3 D4 D5 D6 D7 D8 1 0 00000 000 XXXX X XXX OVERFLOW INHIBITED (GND) OF Dl D2 D3 D4 D5 D6 D7 D8 0 0 11111 111 XXX XX XXX
13 14 15 16 17 18 19 10 11 12 13 14 15 1619 20 21, 22 23 24, 25 26 27 28
HYSTERESIS +VREF ANALOG INPUT ANALOG GROUND ENCODE DIGITAL +VS ANALOG GROUND ANALOG INPUT VR E F R E FMID DIGITAL +VS DIGITAL VS D1 (LSB) D2D5 DIGITAL GROUND ANALOG VS DIGITAL GROUND D6, D7 D8 (MSB) OVERFLOW DIGITAL VS
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change from 5.2 V to 2.2 V at the Hysteresis control pin. The most positive reference voltage for the internal resistor ladder. One of two analog input pins. Both analog input pins should be connected together. One of two analog ground pins. Both analog ground pins should be connected together. TTL level encode command input. ENCODE is rising edge sensitive. One of three positive digital supply pins (nominally +5.0 V). One of two analog ground pins. Both analog ground pins should be connected together. One of two analog input pins. Both analog inputs should be connected together. The most negative reference voltage for the internal resistor ladder. The midpoint tap on the internal resistor ladder. One of three positive digital supply pins (nominally +5.0 V). One of two negative digital supply pins (nominally 5.2 V). Both digital supply pins should be connected together. Digital data output. D1 (LSB) is the least significant bit of the digital output word. Digital data output. One of two digital ground pins. Both digital grounds pins should be connected together. One of two negative analog supply pins (nominally 5.2 V). Both analog supply pins should be connected together. One of two digital ground pins. Both digital ground pins should be connected together. Digital data output. Digital data output D8 (MSB) is the most significant bit of the digital output word. Overflow data output. Logic HIGH indicates an input overvoltage (VIN > + VREF), if OVERFLOW INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT. One of two negative digital supply pins (nominally 5.2 V). Both digital supply pins should be connected together.
PIN CONFIGURATIONS
OVERFLOW INH HYSTERESIS DIGITAL VS+ DIGITAL VS OVERFLOW
OVERFLOW INH HYSTERESIS +VREF ANALOG INPUT ANALOG GROUND ENCODE DIGITAL VS+ ANALOG GROUND
2 3 4 5 6
27 26 25 24 23
OVERFLOW D8 (MSB) D7 D6 DIGITAL GROUND ANALOG VS
ANALOG INPUT 5 ANALOG GROUND 6 ENCODE 7 DIGITAL VS+ 8 ANALOG GROUND 9 ANALOG INPUT 10 VREF 11
4
3
2
1
28 27 26
D8 (MSB)
25 D 7 24 D6 23 DIGITAL GROUND 22 ANALOG VS 21 ANALOG VS 20 DIGITAL GROUND 19 D5
DIGITAL VS+
1
28
DIGITAL VS
+VREF
AD9012
7 22
TOP VIEW 8 (Not to Scale) 21 ANALOG VS
9 20 19 18 17 16 15
AD9012
TOP VIEW (Not to Scale)
DIGITAL GROUND D5 D4 D3 D2 D1 (LSB)
ANALOG INPUT 10 VREF 11 REFMID 12 DIGITAL VS+ 13 DIGITAL VS 14
12 13 14 15 16 17 18
REFMID DIGITAL VS+
D1 (LSB) D2
D3
4
DIGITAL VS
D4
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AD9012
N+1 ANALOG INPUT N APERTURE DELAY ENCODE N+2
t PD
OUTPUT DATA N1 N N+1
Figure 2. Timing Diagram
VREF R 5.0V ANALOG INPUT 5.0V
ENCODE
R/2 REFMID R/2 DIGITAL OUTPUTS
R 5.2V 256 COMPARATOR CELLS VREF
Figure 3. Input Output Circuits
DIE LAYOUT AND MECHANICAL INFORMATION
0.1 F
5.2V
+5.0V 0.1 F
ONE JUMPER PER BOARD AD1 5 100
VS
+ VS OVERFLOW D8 (MSB)
1k 1k 1 1k 1k 1k k 1k 1k 1k LOAD RESISTORS
AIN
AD9012
AD2 2.0V 10 ENCODE VREF VH +VREF DIGITAL GROUND D
D7 D6 D5 D4 D3 D2
D1 (LSB) 1 (LSB) ANALOG GROUND
ALL RESISTORS 5% ALL CAPACITORS 20% ALL SUPPLY VOLTAGES 5% OPTION #1 (STATIC) AD1 = 2.0V; AD2 = +2.4V OPTION #2 (DYNAMIC) SEE WAVEFORMS AD1 640 s 0V 2V +2.4V +0.4V
Die Dimensions . . . . . . . . . . . . . . . . 111 × 123 × 15 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic) Epoxy (Plastic) Bond Wire . . . . . . . . . . . . . 11.3 mil Gold; Gold Ball Bonding
AD2 5s
Figure 4. Burn-In Diagram
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