|Category||Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit|
|Description||ADC, Ttl-compatible Logic: 12-bit|
|Datasheet||Download AD9022 datasheet
FEATURES Monolithic 12-Bit 20 MSPS A/D Converter Low Power Dissipation: 1.4 Watts On-Chip T/H and Reference High Spurious-Free Dynamic Range TTL Logic APPLICATIONS Radar Receivers Digital Communications Digital Instrumentation Electro-Optics
The is a high speed, high performance, monolithic 12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on-chip to provide a complete conversion solution. is a companion unit to the AD9023; the primary difference between the two is that all logic for the AD9022 is TTL-compatible, while the AD9023 utilizes ECL logic for digital inputs and outputs. Pinouts for the two parts are nearly identical. Operating from +5 V and 5.2 V supplies, the AD9022 provides excellent dynamic performance. Sampling at 20 MSPS with AIN = 1 MHz, the spurious-free dynamic range (SFDR) is typically 76 dB; with AIN = 9.6 MHz, SFDR is 74 dB. SNR is typically 65 dB. The onboard T/H has a 110 MHz bandwidth and, more importantly, is designed to provide excellent dynamic performance for analog input frequencies above Nyquist. This feature is necessary in many undersampling signal processing applications, such as in direct IF-to-digital conversion. To maintain dynamic performance at higher IFs, monolithic RF track-and-holds (such as the AD9100 and AD9101 SamplifierTM) can be used with the AD9022 to process signals up to and beyond 70 MHz.
With DNL typically less than 0.5 LSB and 20 ns transient response settling time, the AD9022 provides excellent results when low-frequency analog inputs must be oversampled (such as CCD digitization). The full scale analog input 1 V with a 300 input impedance. The analog input can be driven directly from the signal source, or can be buffered by the AD96xx series of low noise, low distortion buffer amplifiers. All timing is internal to the AD9022; the clock signal initiates the conversion cycle. For best results, the encode command should contain as little jitter as possible. High speed layout practices must be followed to ensure optimum A/D performance. The AD9022 is built on a trench isolated bipolar process and utilizes an innovative multipass architecture (see the block diagram). The unit is packaged in 28-lead ceramic DIPs and gullwing surface mount packages. The AD9022 is specified to operate over the industrial to +85°C) and military to +125°C) temperature ranges.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
Parameter (Conditions) RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Offset Error Gain Error Thermal Noise ANALOG INPUT Input Voltage Range Input Resistance Input Capacitance Analog Bandwidth SWITCHING PERFORMANCE 1 Minimum Conversion Rate Maximum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Delay (tOD) ENCODE INPUT Logic Compatibility Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Pulsewidth (High) Pulsewidth (Low) DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Harmonic Distortion Analog Input @ 1.2 MHz @ 1.2 MHz @ 4.3 MHz @ 9.6 MHz @ 9.6 MHz Signal-to-Noise Ratio 2 Analog Input @ 1.2 MHz @ 1.2 MHz @ 4.3 MHz @ 9.6 MHz @ 9.6 MHz Signal-to-Noise Ratio 2 (Without Harmonics) Analog Input @ 1.2 MHz @ 1.2 MHz @ 4.3 MHz @ 9.6 MHz @ 9.6 MHz +25°C Full +25°C Full +25°C Full +25°C Full VI V Temp(+VS +5 V; VS 5.2 V; Encode = 20 MSPS, unless otherwise noted)
Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full
Parameter (Conditions) Two-Tone Intermodulation Distortion Rejection3 DIGITAL OUTPUTS1 Logic Compatibility Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY +VS Supply Voltage +VS Supply Current VS Supply Voltage VS Supply Current Power Dissipation Power Supply Rejection Ratio (PSRR) 4 Temp +25°C Test Level V AD9022AQ/AZ Min Typ Max 74 TTL Full 2.4 0.5 Offset Binary Offset Binary AD9022BQ/BZ Min Typ Max 74 TTL 2.4 0.5 Offset Binary AD9022SQ/SZ Min Typ Max 74 TTL V Units dBc
NOTES 1 AD9022 load is a single LS latch. 2 RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle. 3 Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz 7 dB below full scale. 4 PSRR is sensitivity of offset error to power supply variations within the 5% limits shown. Specifications subject to change without notice.Model Temperature Range Package Description Package Option Q-28 Z-28
+VS. VS.6 V Analog Input. +1.5 V Digital Inputs. +VS 0 V Digital Output Current. 20 mA Operating Temperature Range to +125°C Maximum Junction Temperature2. +175°C Lead Temperature (Soldering, 10 sec). +300°C Storage Temperature Range. to +150°C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances: "Q" Package (Ceramic DIP): = 35°C/W. "Z" Package (Gullwing Surface Mount): = 45°C/W.
28-Lead Ceramic DIP 28-Pin Ceramic Leaded Chip Carrier +125°C 28-Lead Ceramic DIP +125°C 28-Pin Ceramic Leaded Chip Carrier
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