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Details, datasheet, quote on part number:AD9100S
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Datasheet text preview:
a
FEATURES Ex ellent Hold Mode Distortion into 250 c 88 dB @ 30 MSPS (2.3 MHz VIN) 83 dB @ 30 MSPS (12.1 MHz VIN) 74 dB @ 30 MSPS (19.7 MHz VIN) 16 ns Acquisition Time to 0.01% <1 ps Aperture Jitter 250 MHz Tracking Bandwidth 83 dB Feedthrough Rejection @ 20 MHz 3.3 nV/Hz Spectral Noise Density MlL-STD-Compliant Versions Available APPLICATIONS A/D Conversion Direct IF Sampling Imaging/FLIR Systems Peak Detectors Radar/EW/ECM Spectrum Analysis CCD ATE GENERAL DESCRIPTION
Ultrahigh Speed Monolithic Track-and-Hold AD9100*
FUNCTIONAL BLOCK DIAGRAM
CLK CLK
VIN
50
A1
SWITCH
CHOLD A 22pF
A2
VOUT
2.3V CLAMP
D9100
The AD9100 is a monolithic track-and-hold amplifier which sets a new standard for high speed and high dynamic range applications. It is fabricated in a mature high speed complementary bipolar process. In addition to innovative design topologies, a custom package is utilized to minimize parasitics and optimize dynamic performance. Acquisition time (hold to track) is 13 ns to 0.1% accuracy, and 16 ns to 0.01%. The AD9100 boasts superlative hold-mode frequency domain performance; when sampling at 30 MSPS hold mode distortion is less than 83 dBfs for analog frequencies up to 12 MHz; and 74 dBfs at 20 MHz. The AD9100 can also drive capacitive loads up to 100 pF with little degradation in acquisition time; it is therefore well suited to drive 8- and 10-bit flash converters at clock speeds to 50 MSPS. With a spectral noise density of 3.3 nV/Hz and feedthrough rejection of 83 dB at 20 MHz, the AD9100 is well suited to enhance the dynamic range of many 8- to 16-bit systems.
The AD9100 is "user friendly" and easy to apply: (1) it requires +5 V/5.2 V power supplies; (2) the hold capacitor and switch power supply decoupling capacitors are built into the DIP package; (3) the encode clock is differential ECL to minimize clock jitter; (4) the input resistance is typically 800 k; (5) the analog input is internally clamped to prevent damage from voltage transients. The AD9100 is available in a 20-lead side-brazed "skinny DIP" package. Commercial, industrial, and military temperature grade parts are available. Consult the factory for information about the availability of 883-qualified devices.
PRODUCT HIGHLIGHTS
1. Hold Mode Distortion is guaranteed. 2. Monolithic construction. 3. Analog input is internally clamped to protect against overvoltage transients and ensure fast recovery. 4. Output is short circuit protected. 5. Drives capacitive loads to 100 pF. 6. Differential ECL clock inputs.
*Patent pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
AD9100SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (unless otherwise noted, +V = +5 V; V = 5.2 V; R
S S LOAD = 100
; RIN = 50
)
Units V/V mV mA dB mV/V V µA µA mA pF k k mA V V MHz V/µs V/µs ns dBc dBc µV n V / H z dBfs dBfs dBfs dBfs dBfs V/s rms ± mV/µs ± mV/µs ± mV/µs dB ps ps mV mV mV ns pV-s ns ns ns W mA mA
Parameter DC ACCURACY Gain Offset Output Resistance Output Drive Capability PSRR Pedestal Sensitivity to Supply ANALOG INPUT/OUTPUT Output Voltage Range Input Bias Current Input Overdrive Current2 Input Capacitance Input Resistance CLOCK/CLOCK INPUTS Input Bias Current Input Low Voltage (VIL) Input High Voltage (V IH) TRACK MODE DYNAMICS Bandwidth (3 dB) Slew Rate Overdrive Recovery Time 2 (to 0.1%) 2nd Harm. Dist. (20 MHz, 2 V p-p) 3rd Harm. Dist. (20 MHz, 2 V p-p) Integrated Output Noise (1-200 MHz) RMS Spectral Noise @ 10 MHz HOLD MODE DYNAMICS Worst Harmonic (2.3 MHz, 30 MSPS) Worst Harmonic (12.1 MHz, 30 MSPS) Worst Harmonic (12.1 MHz, 30 MSPS) Worst Harmonic (12.1 MHz, 30 MSPS) Worst Harmonic (19.7 MHz, 30 MSPS) Hold Noise3 Droop Rate4 Feedthrough Rejection (20 MHz) TRACK-TO-HOLD SWITCHING Aperture Delay Aperture Jitter Pedestal Offset Transient Amplitude Settling Time to 1 mV Glitch Product HOLD-TO-TRACK SWITCHING Acquisition Time to 0.1% Acquisition Time to 0.01% Acquisition Time to 0.01% POWER SUPPLY Power Dissipation +VS Current VS Current
Conditions V IN = 2 V V IN = 0 V VS = 0.5 V p-p VS = 0.5 V p-p
Temp Full Full 25° C Full Full Full Full 25° C Full 2 5° C 25° C 2 5 ° C , TMAX T MIN Full Full Full Full 25° C Full 25° C Full Full 25° C 25 ° C 2 5° C 2 5° C TMAX TMIN 2 5° C 2 5° C 25 ° C T MIN T MAX Full 25°C 25°C 25 ° C Full Full Full 25 ° C 25° C Full 25 ° C Full Full Full
Test Level VI VI V VI VI VI VI VI VI V V VI VI VI VI VI IV IV IV V V V V V V IV IV IV V V VI VI VI V V V VI VI V IV V V IV V VI VI VI
AD9100JD/AD/SD1 Min Typ Max 0.989 5 ± 40 48 0.994 ±1 0.4 ± 60 55 0.9 ± 2.2 ±3 ± 22 1.2 800
+5
3 2 +8 +16
VIN = ± 4 V; RIN = 50
+2 8 16 350 200
CL/CL = 1.0 V
4 1.8 1.0 150 550 500 250 850 21 65 75 45 3.3 83 80 77 74 300 1 7 5 83 +800 <1 ±1 ±6 7 15 13 16 20 1.05 96 116
5 1.5 0.8
VOUT 0.4 V p-p 4 V Step 4 V Step VIN = ± 4 V to 0 V
VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p V IN = 0 V VIN = 2 V p-p
72 70 68 tH 10 40 30
V IN = 0 V VIN = 0 V V IN = 0 V 2 V Step 2 V Step 4 V Step
8 10
+8 +10 10
23
1.25 118 132
NOTES 1 AD9100JD: 0°C to +70°C. AD9100AD: 40°C to +85°C. AD9100SD: 55°C to +125°C. DIP JA = 38°C/W; this is valid with the device mounted flush to a grounded 2 oz. copper clad board with 16 sq. inches of surface area and no air flow. 2 The input to the AD9100 is internally clamped at ± 2.3 V. The internal input series resistance is nominally 50 . 3 Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t H) is 20 ns, the accumulated noise is typically 6 µV (300 V/s 2 0 ns). This value must be combined with the track mode noise to obtain total noise. 4 Min and max droop rates are based on the military temperature range (55 °C to +125°C). Refer to the "Droop Rate vs Temperature" chart for min/max limits over the commercial and industrial ranges. Specifications subject to change without notice.
2
REV. B
AD9100
+2V
APERTURE DELAY (0.8ns)
ANALOG INPUT
0V
ACQUISITION TIME (16ns) VOLTAGE LEVEL HELD
2V +2V
HOLD TO TRACK SWITCH DELAY TIME (4ns)
OBSERVED AT HOLD CAPACITOR OBSERVED AT ANALOG OUTPUT
TRACK TO HOLD SETTLING (7ns)
HOLD CAPACITOR/ ANALOG OUTPUT
0V
2V "1"
"HOLD" CLOCK INPUTS CLOCK (PIN #19) CLOCK "TRACK" "HOLD"
"0"
Figure 1. Timing Diagram (1 ns/div)
ABSOLUTE MAXIMUM RATINGS 1 EXPLANATION OF TEST LEVELS
Supply Voltages (± VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . 70 mA Analog Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V Operating Temperature Range (Case) AD9100JD . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD9100AD . . . . . . . . . . . . . . . . . . . . . . . . . 25°C to +85°C AD9100SD . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300°C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Analog input voltage should not exceed ± VS.
Test Level I 100% production tested. II 100% production tested at +25°C, and sample tested at specified temperatures. III Periodically sample tested. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9100 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE
WARNING!
ESD SENSITIVE DEVICE
EVALUATION BOARD ORDERING INFORMATION
Model* AD9100JD AD9100AD AD9100SD
Temperature Range 0°C to +70°C 40°C to +85°C 55°C to +125°C
Package Description Ceramic DIP Ceramic DIP Ceramic DIP
Package Option D-20 D-20 D-20
Part Number AD9100/PWB AD9100/PCB
Description Printed Wiring Board (Only) of Evaluation Circuit Evaluation Board for AD9100T/H, Assembled and Tested [Order AD9100T/H (DIP) Separately]
*Consult factory about availability of parts screened to MIL-STD-883.
REV. B
3
AD9100
PIN FUNCTION DESCRIPTIONS/CONNECTIONS PIN CONFIGURATION 20-Lead Side-Brazed Ceramic DIP
VS GND GND VIN VS BYPASS VS GND VOUT +VS CLK CLK GND
Pin No. 1 2, 3, 8, 1013, 17 4 5, 7 6, 15 9 14, 16, 20 18 19
Description VS GND V IN VS BYPASS V OUT + VS CLK CLK
Connection 5.2 V Power Supply Common Ground Plane Analog Input Signal 5.2 V Power Supply 0.1 µF to Ground Track-and-Hold Output +5 V, Power Supply Complement ECL Clock "True" ECL Clock
AD9100
TOP VIEW (Not to Scale)
+VS BYPASS +VS GND GND GND
CHIP PAD ASSIGNMENTS
+VS +VS 13 CLOCK CLOCK GND 14 15 16 17 12 GND +VS +VS CAP HOLD CAP (NOTE 1) (NOTE 3) +VS +VS NC 3 2 1 32 31 +VS BYPASS (NOTE 2) +VOUT BYPASS (NOTE 2) +VS
GND
NC 11 10
9
8
7
6
5
4
TERMINOLOGY Analog Delay is the time required for an analog input signal to propagate from the device input to output. Aperture Delay tells when the input signal is actually sampled. It is the time difference between the analog propagation delay of the front-end buffer and the control switch delay time. (The time from the hold command transition to when the switch is opened.) For the AD9100, this is a positive value which means that the switch delay is longer than the analog delay. Aperture Jitter is the random variation in the aperture delay. This is measured in ps-rms and results in phase noise on the held signal. Droop Rate is the change in output voltage as a function of time (dV/dt). It is measured at the AD9100 output with the device in hold mode and the input held at a specified dc value, the measurement starts immediately after the T/H switches from track to hold. Feedthrough Rejection is the ratio of the input signal to the output signal when in hold mode. This is a measure of how well the switch isolates the input signal from feeding through to the output. Hold-to-Track Switch Delay is the time delay from the track command to the point when the output starts to change and acquire a new signal. Pedestal Offset is the offset voltage step measured immediately after the AD9100 is switched from track to hold with the input held at zero volts. It manifests itself as an added offset during the hold time. Track-to-Hold Settling Time is the time necessary for the track to hold switching transient to settle to within 1 mV of its final value. Track-to-Hold Switching Transient is the maximum peak switch induced transient voltage which appears at the AD9100 output when it is switched from track to hold.
AD9100
TOP VIEW (Not to scale)
30 29 28 27
18
19
20
21
22
23
24
25
26 VS
VS
NC VIN
VS VS CAP (NOTE 1)
SIZE = 148 63 15 mils NC = NO CONNECT NOTES: 1. SUPPLY BYPASS CAPACITOR; 0.01 TO 0.1 F CERAMIC CONNECTED TO GROUND. 2. 0.01 F CERAMIC CONNECTED BETWEEN PAD 29 AND PAD 31. 3. HOLD CAPACITOR CONNECTED FROM PAD 4 AND PAD 5 TO GROUND; 10100pF, NOMINALLY 22pF. DIP PACKAGE DOES NOT REQUIRE EXTERNAL HOLD CAPACITOR.
4
REV. B
Typical Performance CharacteristicsAD9100
60
0
50 D9100 RS A CL 1k
50
40
PSRR dB
GAIN dB
40 RS
30
5
30
20
20
10 DC 60 120 180 240 INPUT FREQUENCY MHz 300
10
O RS NEEDED WHEN CL IS LESS THAN 6pF
10 DC
N 60 120 180 240 INPUT FREQUENCY MHz 300
0
0
20
40 60 C LOAD pF
80
100
Figure 2. Gain vs. Frequency (Track Mode)
95 VO = 2V p-p ENCODE = 30 MSPS 90 RL = 250
Figure 3. Power Supply Rejection Ratio vs. Frequency
50
Figure 4. Recommended RS vs. CLOAD for Optimal Settling Times
TRACK
40
TRACK
HOLD
2mV/DIV
85
mV/ s
30
dBc
CLK
80 RL = 100 75
20
WORST CASE
CLK
10ns 10 TYPICAL 10ns
70
0
4 8 12 16 INPUT FREQUENCY MHz
20
0 50
+25 +75 0 TEMPERATURE C
+125
100ns/DIV
Figure 5. Worst Hold Mode Harmonic vs. Analog Input Frequency
58
SNR, INCLUDING HARMONICS dB
Figure 6. Magnitude of Droop Rate vs. Temperature
Figure 7. Track-to-Hold-to-Track Switch Transients
58
SNR, INCLUDING HARMONICS dB
AD9060 + AD9100
CH
AD9060 + AD9100
C
CHO
56
LD
= 10pF
O
HO
53
LD
D9100
A AIN CH* 27 10
pF
LD
=
=
22
C
54 AD9060 52 AIN = 3.5V p-p ENCODE = 20 MSPS 50 DC
10
pF
AD9060
FFT PROC
HO
LD
=2
2p
AD9060 48
F
AIN = 3.5V p-p ENCODE = 40 MSPS 43 DC 10 20 30 INPUT FREQUENCY MHz 40
THE AD9060 IS A 10-BIT, 75MSPS MONOLITHIC ADC FROM ANALOG DEVICES. * THE AD9100XD (DIP) HAS AN INTERNAL 22pF HOLD CAPACITOR.
5 10 15 INPUT FREQUENCY MHz
20
Figure 8. SNR vs. Analog Input
105
1.0
Figure 9.
VOUT = 2V STEP
Figure 10. SNR vs. Analog Input
95 BEYOND CAPABILITY OF AVAILABLE MEASUREMENT TOOLS
% OF FULL SCALE
0.1
85 dB 75
0.01
65
55
1
2 10 20 INPUT FREQUENCY MHz
100
0.001 10
12
14
ns
16
18
20
Figure 11. Feedthrough Rejection vs. Input Frequency
Figure 12. Settling Tolerance vs. Acquisition Time
REV. B
5
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