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Details, datasheet, quote on part number:AD9101S
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Datasheet text preview:
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FEATURES 350 MHz Sampling Bandwidth 125 MHz Sampling Rate Excellent Hold Mode Distortion 75 dB @ 50 MSPS (25 MHz V IN) 57 dB @ 125 MSPS (50 MHz VIN) 7 ns Acquisition Time to 0.1% < 1 ps Aperture Jitter 66 dB Feedthrough Rejection @ 50 MHz 3.3 nV/Hz Spectral Noise Density APPLICATIONS Direct IF Sampling Digital Sampling Oscilloscopes HDTV Cameras Peak Detectors Radar/EW/ECM Spectrum Analysis Test Equipment/CCD Testers DDS DAC Deglitcher GENERAL DESCRIPTION
SAMPLER VIN
125 MSPS Monolithic Sampling Amplifier AD9101
FUNCTIONAL BLOCK DIAGRAM
AD9101 +
CHOLD
+
4X AMP
VOUT
3R R
CLOCK
CLOCK
RTN
The AD9101 is an extremely accurate, general purpose, high speed sampling amplifier. Its fast and accurate acquisition speed allows for a wide range of frequency vs. resolution performance. The AD9101 is capable of 8 to 12 bits of accuracy at clock rates of 125 MSPS or 50 MSPS, respectively. This level of performance makes it an ideal driver for almost all 8- to 12-bit A/D encoders on the market today. In effect, the AD9101 is a track-and-hold with a post amplifier. This configuration allows the front end sampler to operate at relatively low signal amplitudes. This results in dramatic improvement in both track and hold mode distortion while keeping power low. The gain-of-four output amplifier has been optimized for fast and accurate large signal step settling characteristics even when heavily loaded. This amplifier's fast Settling Time Linearity (STL) characteristic causes the amplifier to be transparent to the low signal level distortion of the sampler. When sampled, output distortion levels reflect only the distortion performance of the sampler. Dramatic SNR and distortion improvements can be realized when using the AD9101 with high speed flash converters. Flash converters generally have excellent linearity at dc and low frequencies. However, as signal slew rate increases, their performance degrades due to the internal comparators' aperture delay variations and finite gain bandwidth product.
The benefits of using a track-and-hold ahead of a flash converter have been well known for many years. However, before the AD9101, there was no track-and-hold amplifier with sufficient bandwidth and linearity to markedly increase the dynamic performance of such flashes as the AD9002, AD9012, AD9020, and AD9060. A new application made possible by the AD9101 is direct IFto-digital conversion. Utilizing the Nyquist principle, the IF frequency can be rejected, and the baseband signal can be recovered. As an example, a 40 MHz IF is modulated by a 10 MHz bandwidth signal. By sampling at 25 MSPS, the signal of interest is detected. The AD9101 is offered in commercial and military temperature ranges. Commercial versions include the AD9101AR in plastic SOIC and AD9101AE in ceramic LCC. Military devices are available in ceramic LCC. Contact the factory for availability of versions in DIP and/or military versions.
PRODUCT HIGHLIGHTS
1. Guaranteed Hold-Mode Distortion 2. 125 MHz Sampling Rate to 8 Bits; 50 MHz to 12 Bits 3. 350 MHz Sampling Bandwidth 4. Super-Nyquist Sampling Capability 5. Output Offset Adjustable
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD9101SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V = +5 V, V = 5.2 V, R
S S LOAD
= 100
, RlN = 50
Min 3.93 3.9
unless otherwise noted)
AD9101 Typ 4 ±3 0.4 ± 70 43 4 8 ± 2.7 ±5 2 125 Max 4.07 4.1 ± 10 ± 15 Units V/V V/V mV mV mA dB mV/V mV/V V µA µA pF k k mA V V MHz V/µs ns µV µV/Hz dBFS dBFS dBFS dBFS dBFS MHz mV/s mV/µs mV/µs dB ps ps rms mV mV mV ns pV-s ns ns ns mA mA mW REV. 0
Parameter DC ACCURACY Gain Offset Output Resistance Output Drive Capability PSRR Pedestal Sensitivity to Positive Supply Pedestal Sensitivity to Negative Supply ANALOG INPUT/OUTPUT Output Voltage Range Input Bias Current Input Capacitance Input Resistance CLOCK/CLOCK INPUTS Input Bias Current Input Low Voltage (VIL)1 Input High Voltage (VIH)1 TRACK MODE DYNAMICS Bandwidth (3 dB) Slew Rate Overdrive Recovery Time2 (to 0.1%) Integrated Output Noise Input RMS Spectral Noise @ 10 MHz HOLD MODE DYNAMICS Worst Harmonic (23 MHz, 50 MSPS) Worst Harmonic (48 MHz, 100 MSPS) Worst Harmonic (48 MHz, 100 MSPS) Worst Harmonic (48 MHz, 100 MSPS) Worst Harmonic (48 MHz, 125 MSPS) Sampling Bandwidth (3 dB)3 Hold Noise4 (RMS) Droop Rate Feedthrough Rejection (50 MHz) TRACK-TO-HOLD SWITCHING Aperture Delay Aperture Jitter Pedestal Offset Transient Amplitude Settling Time to 4 mV Glitch Product5 HOLD-TO-TRACK SWITCHING Acquisition Time to 0.1% Acquisition Time to 0.01% POWER SUPPLY +VS Current VS Current Power Dissipation
Conditions VIN = 0.5 V VIN = 0.5 V V IN = 0 V V IN = 0 V VS = 0.5 V p-p VS = 0.5 V p-p VS = 0.5 V p-p
Temp 25°C Full 25°C Full 2 5° C Full 2 5° C Full Full Full 2 5° C Full 2 5° C 2 5° C T M A X T MIN
Test Level I VI I VI V VI VI V V VI I VI V VI VI VI VI VI IV IV V V V V IV IV IV V V V I VI V V V I VI V V V V IV IV VI VI VI
± 60 37
± 2.4
± 15 ± 20
30 25
CL/CL = 1.0 V VIN = 0.5 V p-p VIN = 0.5 V p-p VOUT = 1 V p-p 4 Volt Output Step VIN = ± 1 V to 0 V (5 MHz200 MHz)
Full Full Full Full Full 25°C 2 5° C 2 5° C 25°C 25°C Full (Ind.) Full (Mil.) 25°C 2 5° C Full 25°C Full Full 2 5° C 2 5° C 25°C Full Full Full 25°C 2 5° C 2 5° C Full Full Full Full 2
3 1.8 1.0 160 1300 250 1800 55 210 3.3 75 62
3.6 1.5 0.8
VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VIN = 0.5 V p-p
57 53 51
57 350 150 × t H ±5 66 250 <1 ±5 8 4 20 7 11
± 18 ± 40
VOUT = 2 V p-p
V IN = 0 V V IN = 0 V V IN = 0 V V IN = 0 V V IN = 0 V 2 V Output Step 2 V Output Step 2 V Output Step
± 20 ± 35
14 16 70 73 715
55 59 570
AD9101
NOTES 1 If the analog input exceeds ± 300 mV, the clock levels should be shifted as shown in the Theory of Operation section entitled "Driving the Encode Clock." 2 Time to recover within rated error band from 160% overdrive. 3 Sampling bandwidth is defined as the 3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 4 Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t H) is 20 ns, the accumulated noise is typically 3 µV (150 mV/s × 20 ns). This value must be combined with the track mode noise to obtain total noise. 5 Total energy of worst case track-to-hold or hold-to-track glitch. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Pin Description
Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . 0.5 V to +6 V Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . 6 V to +0.5 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V CLOCK/CLOCK Input . . . . . . . . . . . . . . . . . 5 V to +0.5 V Continuous Output Current4 . . . . . . . . . . . . . . . . . . . . 70 mA Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Operating Temperature Range AE, AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to +85°C SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to +125°C Junction Temperature (Ceramic)2 . . . . . . . . . . . . . . . +175°C Junction Temperature (Plastic)2 . . . . . . . . . . . . . . . . +150°C Soldering Temperature (1 minute)3 . . . . . . . . . . . . . . +220°C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (no air flow, soldered to PC board) are as follows: Ceramic LCC: JA = 48°C/W; JC = 9.9°C/W; Plastic SOIC: JA = 54°C/W; JC = 7.3°C/W. 3 For surface mount devices, mounted by vapor phase soldering. Prior to vapor phase soldering, plastic units should receive a minimum eight hour bakeout at 110 °C to drive off any moisture absorbed in plastic during shipping or storage. Through-hole devices can be soldered at +300°C for 10 seconds. 4 Output is short circuit protected to ground. Continuous short circuit may affect device reliability.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Description RTN RTN CB+ + VS + VS GND GND + VS + VS CLK CLK VS VS N/C VIN GND VS VS CB V OUT
Connection Gain Set Resistor Return* Gain Set Resistor Return* Bootstrap Capacitor (Positive Bias) +5 V Power Supply (Analog) +5 V Power Supply (Analog) Hold Capacitor Ground Hold Capacitor Ground +5 V Power Supply (Digital) +5 V Power Supply (Digital) True ECL T/H Clock Complement ECL T/H Clock 5.2 V Power Supply (Digital) 5.2 V Power Supply (Digital) No Connection Analog Signal Input Ground (Signal Return) 5.2 V Power Supply (Analog) 5.2 V Power Supply (Analog) Bootstrap Capacitor (Negative Bias) Analog Signal Output
*See "Matching the AD9101 to A/D Encoders." Both pins should either be grounded or connected to voltage source for offset.
EXPLANATION OF TEST LEVELS Test Level PIN CONFIGURATIONS 20-Pin SOIC
RTN RTN CB+ +VS +VS GND GND +VS +VS 1 2 3 4 5 6 7 8 9 20 VOUT 19 CB 18 V S 17 V S VS VS GND VIN NC 18 17 16 15 14 13 12 11 10 9
VS CLK VS CLK +VS
I 100% production tested. II 100% production tested at +25°C, and sample tested at specified temperatures. III Periodically sample tested. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices.
ORDERING INFORMATION
20-Contact Ceramic LCC
VOUT CB RTN RTN CB+
19 20
1
2
3 4 5 +VS +VS GND GND +VS
BOTTOM VIEW
6 7 8
AD9101
TOP VIEW (Not to Scale)
16 GND 15 V IN 14 NC 13 V S 12 V S 11 CLK
Model AD9101AR AD9101AE AD9101SE
Temperature Range 40°C to +85°C 40°C to +85°C 55°C to +125°C
Package Description Plastic SOIC LCC LCC
Package Option R-20 E-20A E-20A
CLK 10
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9101 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9101
Acquisition Time is the amount of time it takes the AD9101 to reacquire the analog input when switching from hold to track mode. The interval starts at the 50% clock transition point and ends when the input signal is reacquired to within a specified error band at the hold capacitor. Aperture Delay establishes when the input signal is actually sampled. It is the time difference between the analog propagation delay of the front-end buffer and the control switch delay time (the time from the hold command transition to when the switch is opened). For the AD9101, this is a negative value, meaning that the analog delay is longer than the switch delay. Aperture Jitter is the random variation in the aperture delay. This is measured in ps-rms and is manifested as phase noise on the held signal. Droop Rate is the change in output voltage as a function of time (dV/dt). It is measured at the AD9101 output with the device in hold mode and the input held at a specified dc value; the measurement starts immediately after the T/H switches from track to hold. Feedthrough Rejection is the ratio of the output signal to the input signal when in hold mode. This is a measure of how well the switch isolates the input signal from feeding through to the output.
APERTURE DELAY (0.25 ns) VOLTAGE LEVEL HELD ANALOG INPUT (x 4) 0V
Hold-to-Track Switch Delay is the time delay from the track command to the point when the output starts to change to acquire a new signal level. Pedestal Offset is the offset voltage measured immediately after the AD9101 is switched from track to hold with the input held at zero volts. It manifests itself as a dc offset during the hold time. Sampling Bandwidth is the 3 dB frequency response from the input to the hold capacitor under sampling conditions. It is greater than the tracking bandwidth because it does not include the bandwidth of the output amplifier which is optimized for settling time rather than bandwidth. Track-to-Hold Settling Time is the time necessary for the track to hold switching transient to settle to within 4 mV of its final value. Track-to-Hold Switching Transient is the maximum peak switch induced transient voltage which appears at the AD9101 output when it is switched from track to hold.
+2V
ACQUISITION TIME (SEE TEXT) -2V +2V HOLD TO TRACK SWITCH DELAY TIME (1.5 ns) OBSERVED AT HOLD CAPACITOR OBSERVED AT AMPLIFIER OUTPUT 0V TRACK TO HOLD SETTLING (4 ns) -2V CLOCK "1" "HOLD" CLOCK INPUTS "TRACK" "HOLD" CLOCK CLOCK
SAMPLER OUTPUT SIGNAL (x 4) AND AMPLIFIER OUTPUT SIGNAL
"0"
Timing Diagram (500 ps/div)
4
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AD9101
THEORY OF OPERATION
The AD9101 employs a new and unique track-and-hold architecture. Previous commercially available high speed track-andholds used an open loop input buffer, followed by a diode bridge, hold capacitor, and output buffer (closed or open loop) with a FET device usually connected to the hold capacitor. This architecture required mixed device technology and, usually, hybrid construction. The sampling rate of these hybrids has been limited to 20 MSPS for 12-bit accuracy. Distortion generated in the front-end amplifier/bridge limited the dynamic range performance to the "mid 70 dBFS" for analog input signals of less than 10 MHz. Broadband and switch-generated noise limited the SNR of previous track-and-holds to about 70 dB. The AD9101 is a monolithic device using a high frequency complementary bipolar process to achieve new levels of high speed precision. Its architecture completely breaks from the traditional architecture described above. The hold switch has been integrated into the first stage closed-loop buffer. This innovation provides error (distortion) correction for both the switch and buffer while still achieving slew rates representative of an open-loop design. In addition, acquisition slew current for the hold capacitor is higher than the traditional diode bridge switch configurations, removing a main contributor to the limits of maximum sampling rate, input frequency, and distortion. The closed-loop output amplifier includes zero voltage bias current cancellation, which results in high-temperature droop rates close to those found in FET type inputs. This closed-loop amplifier inherently provides high speed loop correction and has extremely low distortion even when heavily loaded. Extremely fast time constant linearity (7 ns to 0.01% for a 4 V output step) ensures that the output amplifier does not limit the AD9101 sampling rate or analog input frequency. (The acquisition and settling time are primarily limited only by the input sampler.) The output is transparent to the overall AD9101 hold mode distortion levels for loads as low as 50 . Full-scale track and acquisition slew rates achieved by the AD9101 are 1800 V/µs and 1700 V/µs, respectively. When combined with excellent phase margin (typically 5% overshoot), wide bandwidth, and dc gain accuracy, acquisition time to 0.01% is only 11 ns.
Acquisition Time
VHC VOUT SAMPLER HC TRACK-TO-HOLD INDUCED GLITCH AMP
VHC VOUT ACQUISITION TIME AT HC TO X% tDHT 1.5ns TS TRACK HOLD
Figure 1. Acquisition Time at Hold Capacitor
during the track time. However, since the output amplifier always "tracks" the front end circuitry, it "catches up" and directly superimposes itself (less about 500 ps of analog delay) to VHC. Since the small signal settling time of the output amplifier can be about 1.2 ns to ± 1 mV, and is significantly less than the hold time, acquisition time should be referenced to the hold capacitor. Most of the hold settling time and output acquisition time are due to the sampler and the switch network. (Output acquisition time is as seen on a scope at the output. This is typically 1.7 ns longer than actual acquisition time.) For track time, the output amplifier contributes only about 5 ns of the total; in hold mode, it contributes 1.7 ns (as stated above). A stricter definition of acquisition would actually include both the acquisition and track-to-hold settling times to a defined accuracy. To obtain 12-bit+ distortion levels and 50 MSPS operation, the minimum recommended track and hold times are 12 ns and 8 ns, respectively. To drive an 8-bit flash converter (such as the AD9002) with a 2 V p-p full-scale input, hold time to 1 LSB accuracy will be limited primarily by the aperture time of the encoder, rather than by the AD9101. This makes it possible to reduce track time to as little as 5 ns, with hold time chosen to optimize the encoder's performance. Though acquisition time and track-to-hold settling time to 1/2 LSB (0.4%) accuracy are 6 ns and 4 ns respectively, it is still possible to achieve 45 dB SNR performance at clock speeds to 125 MSPS. This is because the settling error is roughly proportional to the signal level and is partially cancelled due to the high phase margin of the input sampler.
Hold vs. Track Mode Distortion
Acquisition time is the amount of time it takes the AD9101 to reacquire the analog input when switching from hold-to-track mode. The interval starts at the 50% clock transition point and ends when the input signal is reacquired to within a specified error band at the hold capacitor. The hold-to-track switch delay (tDHT) cannot be subtracted from this acquisition time for 12-bit performance because it is a charging time and analog output delay that occurs when moving from hold to track; this delay is typically 1.5 ns. Therefore, the track time required for the AD9101 is the acquisition time which includes tDHT. Note that the acquisition time is defined as the settled voltage at the hold capacitor and does not include the delay and settling time of the output amplifier. The example in Figure 1 illustrates why the output amplifier does not contribute to the overall acquisition time. The exaggerated illustration in Figure 1 shows that VHC has settled to within x% of its final value, but VOUT (due to slew rate limitations, finite BW, power supply ringing, etc.) has not settled REV. 0
In many traditional high speed, open-loop track-and-holds, track mode distortion is often much better than hold mode distortion. Track mode distortion does not include nonlinearities due to the switch network, and does not correlate to the relevant hold mode distortion. But since hold mode distortion has traditionally been omitted from manufacturer's specification tables, users have had to discover for themselves the effective overall hold mode distortion of the combined T/H and encoder.
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