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Details, datasheet, quote on part number:AD9200JRS
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| Part: | AD9200JRS |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => 10-14 bit |
| Description: | Complete 10-Bit, 20 Msps, 80 MW CMOS A/D Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD9200JRS datasheet File size : 347 kB |
| Request For quote: | Find where to buy AD9200JRS
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Datasheet text preview:
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FEATURES CMOS 10-Bit, 20 MSPS Sampling A/D Converter Pin-Compatible with AD876 Power Dissipation: 80 mW (3 V Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT DESCRIPTION
Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter AD9200
A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. The AD9200 can operate with supply range from 2.7 V to 5.5 V, ideally suiting it for low power operation in high speed portable applications. The AD9200 is specified over the industrial (40°C to +85°C) and commercial (0°C to +70°C) temperature ranges.
PRODUCT HIGHLIGHTS Low Power
The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9200 uses a multistage differential pipeline architecture at 20 MSPS data rates and guarantees no missing codes over the full operating temperature range. The input of the AD9200 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The sample-and-hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit (AD9200ARS, AD9200KST). The dynamic performance is excellent. The AD9200 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.
The AD9200 consumes 80 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW.
Very Small Package
The AD9200 is available in both a 28-lead SSOP and 48-lead LQFP packages.
Pin Compatible with AD876
The AD9200 is pin compatible with the AD876, allowing older designs to migrate to lower supply voltages.
300 MHz On-Board Sample-and-Hold
The versatile SHA input can be configured for either singleended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond the AD9200's input range.
Built-In Clamp Function
Allows dc restoration of video signals with AD9200ARS and AD9200KST.
FUNCTIONAL BLOCK DIAGRAM
CLAMP CLAMP IN CLK AVDD DRVDD
STBY SHA AIN REFTS REFBS REFTF REFBF VREF REFSENSE 1V OUTPUT BUFFERS OTR D9 (MSB) D0 (LSB) AVSS DRVSS
A/D D/A A/D D/A A/D D/A A/D D/A
SHA
GAIN
SHA
GAIN
SHA
GAIN
SHA
GAIN
A/D
MODE
THREESTATE
CORRECTION LOGIC
AD9200
REV. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9200SPECIFICATIONS
Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Reference Input Resistance1 ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (3 dB) Full Power (0 dB) DC Leakage Current INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Load Regulation (1 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption Power-Down Gain Error Power Supply Rejection FS DNL INL EZS E FS REFTS REFBS
(AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted)
Typ 10 20 ± 0.5 ± 0.75 0.4 1.4 1 GND 2 10 4.2 ±1 ±2 1.2 3.5 Max Units Bits MHz LSB LSB % FSR % FSR REFTS = 2.5 V, REFBS = 0.5 V Condition
Symbol Min
AVDD V AVDD 1 V V p-p k k REFTS V pF ns ps MHz µA V mV V mV V V mA mW mW % FS
REFTS, REFBS: MODE = AVDD Between REFTF and REFBF: MODE = AVSS REFBS Min = GND: REFTS Max = AVDD Switched
AIN CIN t AP tAJ BW
REFBS 1 4 2 300 23
Input = ± FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current
VREF VREF
1 ± 10 2 0.5 3 3 26.6 80 4 1
± 25 2 5.5 5.5 33.3 100
AVDD 2.7 DRVDD 2.7 IAVDD PD
AVDD = 3 V, MODE = AVSS AVDD = DRVDD = 3 V, MODE = AVSS STBY = AVDD, MODE and CLOCK = AVSS
PSRR
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz f = 10 MHz Effective Bits f = 3.58 MHz f = 10 MHz Signal-to-Noise SNR f = 3.58 MHz f = 10 MHz Total Harmonic Distortion THD f = 3.58 MHz f = 10 MHz Spurious Free Dynamic Range SFDR f = 3.58 MHz f = 10 MHz Two-Tone Intermodulation Distortion IMD Differential Phase DP Differential Gain DG
54.5
57 54 9.1 8.6
dB dB Bits Bits dB dB dB dB dB dB dB Degree % f = 44.49 MHz and 45.52 MHz NTSC 40 IRE Mod Ramp
55
57 56 66 58 69 61 68 0.1 0.05
59
61
2
REV. E
AD9200
Parameter DIGITAL INPUTS High Input Voltage Low Input Voltage DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency CLAMP 2 Clamp Error Voltage Clamp Pulsewidth
NOTES 1 See Figures 1a and 1b. 2 Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice.
Symbol V IH V IL I OZ t OD t DEN t DHZ VOH VOH VOL VOL VOH VOH VOL VOL t CH t CL
Min 2.4
Typ
Max
Units V V µA ns ns ns V V V V V V V V ns ns Cycles
Condition
0.3 10 25 25 13 +2.95 +2.80 +0.4 +0.05 +4.5 +2.4 +0.4 +0.1 22.5 22.5 3 +10
Output = GND to VDD CL = 20 pF
E OC t CPW
± 20 2
± 40
mV µs
CLAMPIN = 0.5 V2.7 V, R IN = 10 CIN = 1 µF (Period = 63.5 µs)
REFTS
1 10k F
REFTS
AD9200
REFTF 0 .4 VDD REFBF REFBS MODE
AD9200
4.2k
REFBS
0k
AVDD
MODE
igure 1a.
Figure 1b.
REV. E
3
AD9200
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
Min 0.3 0.3 0.3 6.5 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 65
Max +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300
Units V V V V V V V V V V V V °C °C °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD MODE AVSS CLK AVSS Digital Outputs DRVSS AIN AVSS VREF AVSS REFSENSE AVSS REFTF, REFTB AVSS REFTS, REFBS AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec
ORDERING GUIDE Temperature Range Package Description 28-Lead SSOP 28-Lead SSOP 48-Lead LQFP 48-Lead LQFP 28-Lead SSOP (Reel) 28-Lead SSOP (Reel) 48-Lead LQFP (Reel) 48-Lead LQFP (Reel) Evaluation Board Evaluation Board Package Options* RS-28 RS-28 ST-48 ST-48 RS-28 RS-28 ST-48 ST-48
Model
AD9200JRS 0°C to +70°C AD9200ARS 40°C to +85°C AD9200JST 0°C to +70°C AD9200KST 0°C to +70°C AD9200JRSRL 0°C to +70°C AD9200ARSRL 40°C to +85°C AD9200JSTRL 0°C to +70°C AD9200KSTRL 0°C to +70°C AD9200 SSOP-EVAL AD9200 LQFP-EVAL
*RS = Shrink Small Outline; ST = Thin Quad Flatpack.
AVDD DRVDD AVDD AVDD AVDD AVDD
DRVSS DRVSS AVSS AVSS AVSS AVSS AVSS
a. D0D9, OTR
b. Three-State, Standby, Clamp
AVDD REFBS REFTF AVSS AVDD REFBF REFTS AVSS
c. CLK
AVDD
AVDD
AVSS AVDD
AVSS
AVSS
d. AIN
e. Reference
AVDD AVDD
AVDD AVDD
AVSS
AVSS
AVSS
AVSS
f. CLAMPIN
g. MODE
h. REFSENSE
i. VREF
Figure 2. Equivalent Circuits
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. E
AD9200
PIN CONFIGURATIONS 28-Lead Shrink Small Outline (SSOP)
AVSS 1 DRVDD 2 D0 3 D1 4 D2 5 D3 6 28 AVDD 27 AIN 26 VREF 25 REFBS D0 1 D1 2 D2 3 D3 4 D4 5 NC 6 NC 7 D5 8 D6 9 D7 10 D8 11 D9 12 NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 IDENTIFIER 36 35 34 33 32
48-Lead Plastic Thin Quad Flatpack (LQFP)
NC DRVDD AVSS AVDD VREF
AIN
NC
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
NC
NC
NC REFBS REFBF NC MODE NC REFTF REFTS CLAMPIN CLAMP REFSENSE NC
AD9200
24 REFBF 23 MODE
TOP VIEW D4 7 (Not to Scale) 22 REFTF D5 8 D6 9 D7 10 D8 11 D9 12 OTR 13 DRVSS 14 21 REFTS 20 CLAMPIN 19 CLAMP 18 REFSENSE 17 STBY 16 THREE-STATE 15 CLK
AD9200
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
NC
NC
THREE-STATE
OTR
NC
NC
NC
DRVSS
CLK
NC
NC
PIN FUNCTION DESCRIPTIONS
SSOP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
LQFP Pin No. 44 45 1 2 3 4 5 8 9 10 11 12 16 17 22 23 24 26 27 28 29 30 32 34 35 38 39 42
Name AVSS DRVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OTR DRVSS CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVDD
Description Analog Ground Digital Driver Supply Bit 0, Least Significant Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9, Most Significant Bit Out-of-Range Indicator Digital Ground Clock Input HI: High Impedance State. LO: Normal Operation HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp Mode. LO: No Clamp Clamp Reference Input Top Reference Top Reference Decoupling Mode Select Bottom Reference Decoupling Bottom Reference Internal Reference Output Analog Input Analog Supply
REV. E
5
STBY
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