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Details, datasheet, quote on part number:AD9202
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| Part: | AD9202 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => 10-14 bit |
| Description: | Complete 10-bit, 32 Msps, 90 MW CMOS A/D Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD9202 datasheet File size : 351 kB |
| Request For quote: | Find where to buy AD9202
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Datasheet text preview:
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FEATURES CMOS 10-Bit, 32 MSPS Sampling A/D Converter Power Dissipation: 90 mW (3 V Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz Pin-Compatible with the AD9200
Complete 10-Bit, 32 MSPS, 90 mW CMOS A/D Converter AD9202
The AD9202 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. The AD9202 can operate with supply range from 2.7 V to 5.5 V, ideally suiting it for low power operation in high speed portable applications. The AD9202 is specified over the commercial (0°C to +70°C) temperature range.
PRODUCT DESCRIPTION
The AD9202 is a monolithic, single supply, 10-bit, 32 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9202 uses a multistage differential pipeline architecture at 32 MSPS data rates and guarantees no missing codes over the full operating temperature range. The input of the AD9202 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The sample-and-hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit. The dynamic performance is excellent.
PRODUCT HIGHLIGHTS Low Power
The AD9202 consumes 90 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW.
Very Small Package
The AD9202 is available in a 28-lead SSOP package.
300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either singleended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond the input range of the AD9202.
Built-In Clamp Function
Allows dc restoration of video signals.
Pin Compatible with AD9200
The AD9202 allows "drop-in" upgrade for AD9200 users.
FUNCTIONAL BLOCK DIAGRAM
CLAMP CLAMP IN CLK AVDD DRVDD
STBY SHA AIN REFTS REFBS REFTF REFBF VREF REFSENSE 1V OUTPUT BUFFERS OTR D9 (MSB) D0 (LSB) AVSS DRVSS
A/D D/A A/D D/A A/D D/A A/D D/A
SHA
GAIN
SHA
GAIN
SHA
GAIN
SHA
GAIN
A/D
MODE
THREESTATE
CORRECTION LOGIC
AD9202
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9202SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, T
Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity @ 32 MHz @ 27 MHz Integral Nonlinearity @ 32 MHz @ 27 MHz Offset Error @ 32 MHz @ 27 MHz Gain Error @ 32 MHz @ 27 MHz REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Reference Input Resistance1 ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Full Power Bandwidth DC Leakage Current INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Load Regulation (1 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption @ 32 MSPS @ 27 MSPS Power-Down FS DNL INL EZS E FS ± 0.5 ± 0.5 ± 1.0 ± 0.5 ± 0.8 ± 0.5 ± 0.5 ± 0.5 1 GND 2 10 4.2 AIN CIN t AP tAJ FPBW REFBS 1 4 2 300 23 REFTS Symbol Min Typ 10 32 ±1 ± 2.9 ± 2.3 ± 2.1 Max Units Bits MHz LSB LSB % FSR % FSR
(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input MIN to TMAX unless otherwise noted)
Conditions
REFTS = 2.5 V, REFBS = 0.5 V
REFTS REFBS
AVDD AVDD-1
V V V p-p k k V pF ns ps MHz µA
REFTS, REFBS: MODE = AVDD Between REFTF & REFBF: MODE = AVSS REFBS Min = GND: REFTS Max = AVDD Switched
I n p u t = ± FS
VREF
1 ± 15 ± 21
V mV V ± 1.0 5.5 5.5 38 115 mV V V mA mW mW
REFSENSE = VREF
VREF
2 ± 0.5
REFSENSE = GND 1 mA Load Current
AVDD 2.7 DRVDD 2.7 IAVDD PD
3 3 29.9 90 86 3.5
AVDD = 3 V, MODE = AVSS AVDD = DRVDD = 3 V, MODE = AVSS STBY = AVDD, MODE = AVSS
Gain Error Power Supply Rejection
DIGITAL INPUTS High Input Voltage Low Input Voltage DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay
PSRR
V IH V IL I OZ tOD tDEN t DHZ 2.4
± 0.3
% FS
V V µA ns ns ns Output = GND to VDD CL = 20 pF
0.3 10 25 25 13 +10
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AD9202
Parameter LOGIC OUTPUT (with DRVDD = +3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) LOGIC OUTPUT (with DRVDD = +5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency CLAMP Clamp Error Voltage Clamp Pulsewidth
NOTES 1 See Figures 1a and 1b. Specifications subject to change without notice.
Symbol VOH VOH VOL
Min +2.95 +2.80
Typ
Max
Units V V V V V V V V ns ns Cycles
Conditions
VOL
VOH VOH VOL +4.5 +2.4
+0.4 +0.5
VOL
tCH tCL 14.7 14.7 3 EOC tCPW ± 20 2
+0.4 +0.5
± 40
mV µs
CLAMPIN = 0.5 V2.7 V, RIN = 10 CIN = 1 µF (Period = 63.5 µs)
REFTS
1 10k F 0k
REFTS
AD9202
REFTF 0 .4 V DD
AD9202
4.2k REFBF REFBS MODE
REFBS
AV DD
MODE
a.
b.
igure 1. REFT and REFB Equivalent Circuits
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3
AD9202SPECIFICATIONS External Reference, T
Parameter Symbol Min Typ Max
(AVDD = +3 V, DRVDD = +3 V, MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, MIN to TMAX unless otherwise noted)
Min Typ Max Units Conditions
CONVERSION RATE DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion f = 3.58 MHz f = 13.5 MHz f = 16 MHz Effective Bits f = 3.58 MHz f = 13.5 MHz f = 16 MHz Signal-to-Noise Ratio f = 3.58 MHz f = 13.5 MHz f = 16 MHz Total Harmonic Distortion f = 3.58 MHz f = 13.5 MHz f = 16 MHz Spurious Free Dynamic Range f = 3.58 MHz f = 10 MHz f = 16 MHz Two-Tone Intermodulation Distortion1 Differential Phase Differential Gain
FS
27
32
MSPS
SINAD 58 55.4 53.7 55.7 54.3 9.3 8.9 SNR 58.9 58.8 THD 65.6 55.8 SFDR 68.3 59 58 67 58.8 IMD DP DG 65 0.1 0.05 74 0.1 0.05 dB dB dB dB Degree NTSC 40 IRE Mode Ramp % 64.5 57.6 57 dB dB dB 54.2 56.4 56.4 dB dB dB 8.6 9.0 8.7 dB dB dB Bits Bits Bits
NOTES 1 At FS = 27 MHz, fIN = 69.5 MHz and 70.5 MHz; at F S = 32 MHz, f IN = 44.5 MHz and 45.5 MHz; REFBS = 1 V, REFTS = 2 V (Figure 16a). Specifications subject to change without notice.
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AD9202
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD DRVDD AVSS AVDD MODE CLK Digital Outputs AIN VREF REFSENSE REFTF, REFTB REFTS, REFBS Junction Temperature Storage Temperature Lead Temperature 10 sec
With Respect to AVSS DRVSS DRVSS DRVDD AVSS AVSS DRVSS AVSS AVSS AVSS AVSS AVSS
Min Max 0.3 0.3 0.3 6.5 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 65 +150 +300
Units V V V V V V V V V V V V °C °C °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
ORDERING GUIDE Temperature Range Package Description Package Options*
Model
AD9202JRS 0°C to +70°C AD9202JRSRL 0°C to +70°C AD9202-EVAL
*RS = Shrink Small Outline.
28-Lead SSOP RS-28 28-Lead SSOP (Reel) RS-28 Evaluation Board
AVDD DRVDD AVDD AVDD AVDD AVDD
DRVSS DRVSS AVSS AVSS AVSS AVSS AVSS
a. D0D9, OTR
b. Three-State, Standby, Clamp
AVSS AVDD REFBS REFTF AVSS AVDD REFBF REFTS AVSS
c. CLK
AVDD
AVDD
AVSS AVDD
AVSS
AVSS
d. AIN
e. Reference
AVDD AVDD
AVDD AVDD
AVSS
AVSS
AVSS
AVSS
f. CLAMPIN
g. MODE
h. REFSENSE
i. VREF
Figure 2. Equivalent Circuits
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9202 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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