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Details, datasheet, quote on part number:AD9203ARU
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| Part: | AD9203ARU |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => <10 bit |
| Description: | 10-Bit, 40 Msps, Low-power Analog-to-digital Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD9203ARU datasheet File size : 819 kB |
| Request For quote: | Find where to buy AD9203ARU
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Datasheet text preview:
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FEATURES CMOS 10-Bit 40 MSPS Sampling A/D Converter Power Dissipation: 74 mW (3 V Supply, 40 MSPS) 17 mW (3 V Supply, 5 MSPS) Operation Between 2.7 V and 3.6 V Supply Differential Nonlinearity: 0.25 LSB Power-Down (Standby) Mode, 0.65 mW ENOB: 9.55 @ fIN = 20 MHz Out-of-Range Indicator Adjustable On-Chip Voltage Reference IF Undersampling up to f IN = 130 MHz Input Range: 1 V to 2 V p-p Differential or Single-Ended Adjustable Power Consumption Internal Clamp Circuit APPLICATIONS CCD Imaging Video Portable Instrumentation IF and Baseband Communications Cable Modems Medical Ultrasound PRODUCT DESCRIPTION
CLAMP CLAMPIN AINP AINN
10-Bit, 40 MSPS, 3 V, 74 mW A /D Converter AD9203
FUNCTIONAL BLOCK DIAGRAM
CLK AVDD DRVDD
AD9203
A/D SHA A/D D/A GAIN A/D SHA D/A GAIN
STBY
3 STATE
REFTF REFBF BANDGAP REFERENCE
+
CORRECTION LOGIC
OUTPUT BUFFERS 10
OTR D9 (MSB) D0 (LSB)
VREF REFSENSE 0.5V AVSS
PWRCON
DFS
DRVSS
The AD9203 is a monolithic low power, single supply, 10-bit, 40 MSPS analog-to-digital converter, with an on-chip voltage reference. The AD9203 uses a multistage differential pipeline architecture and guarantees no missing codes over the full operating temperature range. Its input range may be adjusted between 1 V and 2 V p-p. The AD9203 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of an application. An external resistor can be used to reduce power consumption when operating at lower sampling rates. This yields power savings for users who do not require the maximum sample rate. This feature is especially useful at sample rates far below 40 MSPS. Excellent performance is still achieved at reduced power. For example, 9.7 ENOB performance may be realized with only 17 mW of power, using a 5 MHz clock. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary or two's complementary output format by using the DFS pin. An out-of-range signal (OTR) indicates an overflow condition that can be used with the most significant bit to determine over or under range.
The AD9203 can operate with a supply range from 2.7 V to 3.6 V, attractive for low power operation in high-speed portable applications. The AD9203 is specified over industrial (40°C to +85°C) temperature ranges and is available in a 28-lead TSSOP package.
PRODUCT HIGHLIGHTS Low Power
The AD9203 consumes 74 mW on a 3 V supply operating at 40 MSPS. In standby mode, power is reduced to 0.65 mW.
High Performance
Maintains better than 9.55 ENOB at 40 MSPS input signal from dc to Nyquist.
Very Small Package
The AD9203 is available in a 28-lead TSSOP.
Programmable Power
The AD9203 power can be further reduced by using an external resistor at lower sample rates.
Built-In Clamp Function
Allows dc restoration of video signals.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9203SPECIFICATIONS Reference, PWRCON = AVDD, 50% clock duty cycle, T
Parameter RESOLUTION MAX CONVERSION RATE PIPELINE DELAY DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (3 dB) Input Referred Noise INTERNAL REFERENCE Output Voltage (0.5 V Mode) Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Load Regulation POWER SUPPLY Operating Voltage Analog Supply Current Digital Supply Current Power Consumption Power-Down Power Supply Rejection Ratio DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion f = 4.8 MHz f = 20 MHz Effective Bits f = 4.8 MHz f = 20 MHz Signal-to-Noise Ratio f = 4.8 MHz f = 20 MHz Total Harmonic Distortion f = 4.8 MHz f = 20 MHz Spurious Free Dynamic Range f = 4.8 MHz f = 20 MHz Two-Tone Intermodulation Distortion Differential Phase Differential Gain DIGITAL INPUTS High Input Voltage Low Input Voltage Clock Pulsewidth High Clock Pulsewidth Low Clock Period2 PD PSRR DNL INL E ZS E FS AIN CIN T AP TA J BW 1 1.4 2.0 1.2 390 0.3 0.5 1 ±5 0.65 2.7 2.7 3.0 3.0 20.1 4.4 9.5 74 88.8 0.65 0.04 ± 0.25 ± 0.65 ± 0.6 ± 0.7 FS 40 5.5 ± 0.7 ± 1.4 ± 2.8 ± 4.0 2 Symbol Min Typ 10 Max Unit Bits MSPS Clock Cycles LSB LSB % FSR % FSR V p-p pF ns ps rms MHz mV V V mV mV V V mA mA mA mW mW mW % FS
(AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, Internal 1 V MIN to TMAX unless otherwise noted.)
Conditions
Switched, Single-Ended
VREF VREF
REFSENSE = VREF REFSENSE = GND 1.0 mA Load
± 30 1.2 3.6 3.6 22.0 6.0 14.0 84.0 108.0 1.2 ± 0.25
AVDD DRVDD IAVDD IDRVDD
fIN = 4.8 MHz, Output Bus Load = 10 pF fIN = 20 MHz, Output Bus Load = 20 pF fIN = 4.8 MHz, Output Bus Load = 10 pF fIN = 20 MHz, Output Bus Load = 20 pF
SINAD 57.2 ENOB 9.2 SNR 57.5 THD 76.0 74.0 65.0 SFDR 67.8 IMD DP DG V IH V IL 2.0 0.4 11.25 11.25 25 80 78 68 0.2 0.3 dB dB dB Degree % V V ns ns ns dB dB 60.0 59.5 dB dB 9.6 9.55 Bits Bits 59.7 59.3 dB dB
Note 1
Note 1
Note 1
Note 1 f = 44.49 MHz and 45.52 MHz NTSC 40 IRE Ramp
2
REV. A
AD9203
Parameter DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) Symbol I OZ t OD t DEN t DHZ VOH VOH VOL VOL 2.95 2.80 0.3 0.05 Min Typ Max ± 5.0 5 6 6 Unit µA ns ns ns V V V V Conditions Output = 0 to DRVDD CL = 20 pF CL = 20 pF CL = 20 pF
NOTES 1 Differential Input (2 V p-p). 2 The AD9203 will convert at clock rates as low as 20 kHz. Specifications subject to change without notice.
N ANALOG INPUT N1
N+1 N+2 N+3 N+4 N+6 N+5
CLOCK DATA OUT
N7
N6
N5
N4
N3
N2
N1
N
N+1
TOD = 3ns MIN 7ns MAX (CLOAD = 20pF)
Figure 1. Timing Diagram
REV. A
3
AD9203
ABSOLUTE MAXIMUM RATINGS*
With Respect to Min AVSS DRVSS DRVSS DRVDD AVSS AVSS DRVSS AINN AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS 0.3 0.3 0.3 3.9 0.3 0.3 0.3 AVSS 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 65
THERMAL CHARACTERISTICS
Parameter AVDD DRVDD AVSS AVDD REFCOM CLK Digital Outputs AINP VREF REFSENSE REFTF, REFBF STBY CLAMP CLAMPIN PWRCON DFS 3-STATE Junction Temperature Storage Temperature Lead Temperature (10 sec)
Max +3.9 +3.9 +0.3 +3.9 +0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 +150 300
Unit V V V V V V V V V V V V V V V V V °C °C °C
28-Lead TSSOP JA = 97.9°C/W JC = 14.0°C/W
ORDERING GUIDE Temperature Range Package Description Package Option
Model
AD9203ARU 40°C to +85°C AD9203-EB
28-Lead Thin Shrink RU-28 Small Outline Evaluation Board
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9203 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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REV. A
AD9203
PIN CONFIGURATION
DRVSS 1 DRVDD 2 (LSB) D0 3 D1 4 D2 5 D3 6 D4 7 28 AVDD 27 AVSS 26 AINN 25 AINP 24 REFBF
AD9203
23 VREF
TOP VIEW 22 REFTF D5 8 (Not to Scale) 21 PWRCON D6 9 D7 10 D8 11 20 CLAMPIN 19 CLAMP 18 REFSENSE 17 STBY 16 3-STATE 15 CLK
(MSB) D9 12 OTR 13 DFS 14
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name DRVSS DRVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OTR DFS CLK 3-STATE STBY REFSENSE CLAMP CLAMPIN PWRCON REFTF VREF REFBF AINP AINN AVSS AVDD
Description Digital Ground Digital Supply Bit 0, Least Significant Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9, Most Significant Bit Out-of-Range Indicator Data Format Select. (HI: Two's Complement. LO: Straight Binary) Clock Input HI: High Impedance State Output. LO: Active Digital Output Drives HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp. LO: Open Clamp Clamp Signal Input Power Control Input Top Reference Decoupling Reference In/Out Bottom Reference Decoupling Noninverting Analog Input Inverting Analog Input Analog Ground Analog Supply
REV. A
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