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Details, datasheet, quote on part number:AD9280
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| Part: | AD9280 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => <10 bit |
| Description: | 8-Bit, Complete, 32 MSPS A/D Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD9280 datasheet File size : 375 kB |
| Request For quote: | Find where to buy AD9280
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Datasheet text preview:
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FEATURES CMOS 8-Bit 32 MSPS Sampling A/D Converter Pin-Compatible with AD876-8 Power Dissipation: 95 mW (3 V Supply) Operation Between +2.7 V and +5.5 V Supply Differential Nonlinearity: 0.2 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT DESCRIPTION
Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter AD9280
A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. The AD9280 can operate with a supply range from +2.7 V to +5.5 V, ideally suiting it for low power operation in high speed applications. The AD9280 is specified over the industrial (40°C to +85°C) temperature range.
PRODUCT HIGHLIGHTS Low Power
The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9280 uses a multistage differential pipeline architecture at 32 MSPS data rates and guarantees no missing codes over the full operating temperature range. The input of the AD9280 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The sample-and-hold amplifier (SHA) is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC-coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit. The dynamic performance is excellent. The AD9280 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.
The AD9280 consumes 95 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW.
Very Small Package
The AD9280 is available in a 28-lead SSOP package.
Pin Compatible with AD876-8
The AD9280 is pin compatible with the AD876-8, allowing older designs to migrate to lower supply voltages.
300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either singleended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond the AD9280's input range.
Built-In Clamp Function
Allows dc restoration of video signals.
FUNCTIONAL BLOCK DIAGRAM
CLAMP CLAMP IN CLK AVDD DRVDD
STBY SHA VINA REFTF REFTS REFBS REFBF OUTPUT BUFFERS VREF REFSENSE 1V
A/D D/A A/D D/A A/D D/A A/D D/A
SHA
GAIN
SHA
GAIN
SHA
GAIN
SHA
GAIN
A/D
MODE
THREESTATE
CORRECTION LOGIC OTR D7 (MSB) D0 (LSB) AVSS DRVSS
AD9280
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9280SPECIFICATIONS
Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Reference Input Resistance1 ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (3 dB) Full Power (0 dB) DC Leakage Current INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Load Regulation (1 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption Power-Down Gain Error Power Supply Rejection FS DNL INL EZS EF S REFTS REFBS Symbol
(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted)
Min Typ 8 32 ± 0.2 ± 0.3 ± 0.2 ± 1.2 1 GND 2 10 4.2 ± 1.0 ± 1.5 ± 1.8 ± 3.9 Max Units Bits MHz LSB LSB % FSR % FSR REFTS = 2.5 V, REFBS = 0.5 V Condition
AVDD V AVDD 1 V V p-p k k REFTS V pF ns ps MHz µA V mV V mV V V mA mW mW % FS
REFTS, REFBS: MODE = AVDD Between REFTF & REFBF: MODE = AVSS REFBS Min = GND: REFTS Max = AVDD Switched
AIN CIN tAP tAJ BW
REFBS 1 4 2 300 43
Input = ± FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current
VREF VREF
1 ± 10 2 0.5 2.7 2.7 3 3 31.7 95 4 1
± 25 2 5.5 5.5 36.7 110
AVDD DRVDD IAVDD PD
AVDD = 3 V, MODE = AVSS AVDD = DRVDD = 3 V, MODE = AVSS STBY = AVDD, MODE and CLOCK = AVSS
PSRR
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz f = 16 MHz Effective Bits f = 3.58 MHz f = 16 MHz Signal-to-Noise SNR f = 3.58 MHz f = 16 MHz Total Harmonic Distortion THD f = 3.58 MHz f = 16 MHz Spurious Free Dynamic Range SFDR f = 3.58 MHz f = 16 MHz Differential Phase DP Differential Gain DG
46.4
49 48 7.8 7.7
dB dB Bits Bits dB dB 49.5 dB dB dB dB Degree %
47.8
49 48 62 58 66 61 0.2 0.08
51.4
NTSC 40 IRE Mod Ramp
2
REV. D
AD9280
Parameter DIGITAL INPUTS High Input Voltage Low Input Voltage DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency CLAMP Clamp Error Voltage Clamp Pulsewidth
NOTES 1 See Figures 1a and 1b. Specifications subject to change without notice.
Symbol V IH V IL I OZ t OD t DEN t DHZ VOH VOH VOL VOL VOH VOH VOL VOL tCH tCL
Min 2.4
Typ
Max
Units V V µA ns ns ns V V V V V V V V ns ns Cycles
Condition
0.3 10 25 25 13 +2.95 +2.80 +0.4 +0.05 +4.5 +2.4 +0.4 +0.1 14.7 14.7 3 +10
Output = GND to VDD CL = 20 pF
EOC t CPW
± 60 2
± 80
mV µs
CLAMPIN = +0.5 V to +2.0 V, RIN = 10 CIN = 1 µF (Period = 63.5 µs)
1 10k REFTS 0k REFBS
REFTS
AD9280
REFTF 0 .4 VDD
AD9280
4.2k REFBF REFBS MODE
AVDD
MODE
a. Figure 1. Equivalent Input Load
b.
REV. D
3
AD9280
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
Min 0.3 0.3 0.3 6.5 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 65
Max +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300
Units V V V V V V V V V V V V °C °C °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD MODE AVSS CLK AVSS Digital Outputs DRVSS AIN AVSS VREF AVSS REFSENSE AVSS REFTF, REFTB AVSS REFTS, REFBS AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec
ORDERING GUIDE Temperature Range Package Description Package Option*
Model
AD9280ARS 40°C to +85°C 28-Lead SSOP RS-28 AD9280ARSRL 40°C to +85°C 28-Lead SSOP (Reel) RS-28 AD9280-EB Evaluation Board
*RS = Shrink Small Outline.
AVDD DRVDD AVDD AVDD AVDD AVDD
DRVSS DRVSS AVSS AVSS AVSS AVSS AVSS
a. D0D7, OTR
b. Three-State, Standby, Clamp
AVDD
c. CLK
AVDD
AVDD
REFBS
25
REFTF
AVSS
22
AVSS AVDD
AVDD
REFBF
AVSS
24
REFTS
AVSS
21
AVSS
d. AIN
AVDD AVDD
e. Reference
AVDD AVDD
AVSS
AVSS
AVSS
AVSS
f. CLAMPIN
g. MODE
h. REFSENSE
i. VREF
Figure 2. Equivalent Circuits
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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REV. D
AD9280
PIN CONFIGURATION 28-Lead Wide Body (SSOP)
AVSS 1 DRVDD 2 NC 3 NC 4 D0 5 D1 6
28 AVDD 27 AIN 26 VREF 25 REFBS
AD9280
24 REFBF
TOP VIEW 23 MODE D2 7 (Not to Scale) 22 REFTF
D3 8 D4 9 D5 10 D6 11 D7 12 OTR 13 DRVSS 14
21 REFTS 20 CLAMPIN 19 CLAMP 18 REFSENSE 17 STBY 16 THREE-STATE 15 CLK
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
SSOP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name AVSS DRVDD NC NC D0 D1 D2 D3 D4 D5 D6 D7 OTR DRVSS CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVDD
Description Analog Ground Digital Driver Supply No Connect No Connect Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7, Most Significant Bit Out-of-Range Indicator Digital Ground Clock Input HI: High Impedance State. LO: Normal Operation HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp Mode. LO: No Clamp Clamp Reference Input Top Reference Top Reference Decoupling Mode Select Bottom Reference Decoupling Bottom Reference Internal Reference Output Analog Input Analog Supply
REV. D
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