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Details, datasheet, quote on part number:AD9283BRS-50
 
 
Part:AD9283BRS-50
Category:Data Conversion => ADC (Analog to Digital Converters) => <10 bit
Description:8-Bit, 50 MSPS/80 MSPS/100 MSPS ADC
Company:Analog Devices
Datasheet:Download AD9283BRS-50 datasheet   File size : 259 kB
Request For quote:  Find where to buy AD9283BRS-50
 



Datasheet text preview:
a
FEATURES 8-Bit, 50, 80, and 100 MSPS ADC Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth SNR = 46.5 dB @ 41 MHz at 100 MSPS 1 V p-p Analog Input Range Single 3.0 V Supply Operation (2.7 V­3.6 V) Power-Down Mode: 4.2 mW APPLICATIONS Battery Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes

8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D Converter AD9283
FUNCTIONAL BLOCK DIAGRAM
VD PWRDWN VDD

AD9283
AIN AIN ENCODE TIMING REF T/H ADC OUTPUT STAGING 8 D7­D0

GND

REF REF OUT IN

GENERAL DESCRIPTION

The AD9283 is an 8-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is optimized for low cost, low power, small size and ease of use. The product operates at a 100 MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.

The encoder input is TTL/CMOS compatible. A power-down function may be exercised to bring total consumption to 4.2 mW. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9283 is available in a 20-lead surface mount plastic package (SSOP) specified over the industrial temperature range (­40°C to +85°C).

REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

AD9283­SPECIFICATIONS (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY Power Dissipation3, 4 Power-Down Dissipation Power Supply Rejection Ratio (PSRR) 25°C Full 25°C Full Full 25°C Full Full I VI I VI VI I VI VI Temp Test Level

DD = 3.0 V, VD = 3.0 V; single-ended input; external

reference, unless otherwise noted)
AD9283BRS-50 Min Typ Max 8 Unit Bits +1.25 +1.50 +1.25 +1.50 +6 +8 LSB LSB LSB LSB % FS % FS ppm/ °C

AD9283BRS-100 Min Typ Max 8 ± 0.5 ­1.25 ± 0.75 +1.25 +1.50 +1.25 +2.25 +6 +8

AD9283BRS-80 Min Typ Max 8 ± 0.5 ­1.25 ± 0.75 +1.25 +1.50 +1.25 +1.50 +6 +8

± 0.5 ­1.25 ± 0.75

Guaranteed ­6 ± 2.5 ­8 80

­6 ­8

Guaranteed ± 2.5 80

­6 ­8

Guaranteed ± 2.5 80

Full Full 25°C Full Full Full 25° C Full 25° C Full 25°C Full 25°C 25°C 25°C 25°C 25° C Full Full Full Full Full Full 25° C Full Full

V V I VI VI VI I VI V VI V VI IV IV IV V V VI VI VI VI VI VI V VI VI

­35 1.2 7 5

± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 2 475

+35 1.3 13 16

­35 1.2 7 5

± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 2 475

+35 1.3 13 16

­35 1.2 7 5

± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 2 475

+35 1.3 13 16

mV p-p mV mV mV V ppm/ °C k k pF µA MHz MSPS MSPS ns ns ns ps rms ns ns V V µA µA pF V V

100 4.3 4.3 0 5 3.0 4.5 1 1000 1000

80 5.0 5.0 0 5 3.0 4.5 1 1000 1000

50 8.0 8.0 0 5 3.0 4.5 1 1000 1000

2.0

2.0 7.0 2.0 0.8 ±1 ±1

2.0 7.0 2.0 0.8 ±1 ±1

7.0

2.0

0.8 ±1 ±1 2.0 2.95 0.05 Offset Binary Code 80 4.2 100 7 18

2.0 2.95 0.05 Offset Binary Code 90 4.2 120 7 18 2.95

2.0

0.05 Offset Binary Code 90 4.2 115 7 18

Full Full 25°C

VI VI I

mW mW mV/V

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REV. C

AD9283
Parameter DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz
5

Temp 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 2 5° C 25°C

Test Level V V

AD9283BRS-100 Min Typ Max 2 2

AD9283BRS-80 Min Typ Max 2 2

AD9283BRS-50 Min Typ Max 2 2

Unit ns ns

I I I V

46.5 46.5 43.5 46.5 46.0

44

47 47 47

44

47 47

dB dB dB dB

I I I V I I I V I I I V I I I V

45 45.5 42.5 45 42.5 7.3 7.4 7.3 6.9 57 60 58 46 54.5 55 52.5 53

47 43.5 46.5 42

43.5 46.5 46

dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc

7.5 7.5 7.5

7.6 7.5

55

50

60 60 55

55

60 56

55

47

70 62.5 60

55

70 60

V

52

52

52

dBc

NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 µA. 3 Power dissipation measured with encode at rated speed and a dc analog input. 4 Typical thermal impedance for the RS style (SSOP) 20-lead package: JC = 46°C/W, CA = 80°C/W, JA = 126°C/W. 5 SNR/harmonics based on an analog input voltage of ­0.7 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . . . . . . . . . . . ­0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . ­0.5 V to VDD + 0.5 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . . ­0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . ­55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . ­65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

Model

Temperature Ranges

Package Descriptions

Package Options

AD9283BRS -50, -80, -100 ­40°C to +85°C 20-Lead SSOP RS-20 AD9283/PCB 25°C Evaluation Board

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9283 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!
ESD SENSITIVE DEVICE

REV. C

­3­

AD9283
EXPLANATION OF TEST LEVELS Table I. Output Coding (VREF = 1.25 V)

Test Level I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

Step 255 · · 128 127 · · 0

AIN­AIN 0.512 · · 0.002 ­0.002 · · ­0.512

Digital Output 1111 1111 · · 1000 0000 0111 1111 · · 0000 0000

PIN CONFIGURATION
D0 (LSB) D1 D2 D3 GND

PWRDWN 1 VREF OUT 2 VREF IN 3 GND 4 VD 5 A IN 6

20 19 18 17

AD9283

16

TOP VIEW 1 5 V DD (Not to Scale) 1 4 D4 A IN 7 VD 8 GND 9 ENCODE 1 0
13 12 11

D5 D6 D7 (MSB)

PIN FUNCTION DESCRIPTIONS

Pin Number 1 2 3 4, 9, 16 5, 8 6

Mnemonic PWRDWN VREF OUT VREF IN GND VD AIN

Function Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to High Impedance State) Internal Reference Output (1.25 V typ); Bypass with 0.1 µF to Ground Reference Input for ADC (1.25 V typ) Ground Analog 3 V Power Supply Analog Input for ADC (Can Be Left Open if Operating in Single-Ended Mode, but Recommend Connection to a 0.1 µF Capacitor and a 25 Resistor in Series to Ground for Better Input Matching) Analog Input for ADC Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE) Digital Outputs of ADC Digital output power supply. Nominally 2.5 V to 3.6 V

7 10 11­14, 17­20 15

AIN ENCODE D7­D4, D3­D0 V DD

­4­

REV. C

AD9283
SAMPLE N AIN SAMPLE N+1 SAMPLE N+4 SAMPLE N+5

tA tEH
ENCODE

SAMPLE N+2

SAMPLE N+3

tEL

1/fS

t PD
D7­D0 DATA N­4 DATA N­3 DATA N­2 DATA N­1 DATA N

tV
DATA N+1

Figure 1. Timing Diagram
VDD
VDD 1 33.3k 13.3k

OUT

A IN 4.3F k

AIN 34.3k

igure 2. Equivalent Analog Input Circuit
VD

Figure 5. Equivalent Digital Output Circuit

VD

VBIAS

REF IN

OUT

Figure 3. Equivalent Reference Input Circuit
VD

Figure 6. Equivalent Reference Output Circuit

ENCODE

Figure 4. Equivalent Encode Input Circuit

REV. C

­5­