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Details, datasheet, quote on part number:AD9288
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| Part: | AD9288 |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => <10 bit |
| Description: | 8-Bit, 40/80/100 MSPS Dual A/D Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD9288 datasheet File size : 445 kB |
| Request For quote: | Find where to buy AD9288
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Datasheet text preview:
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FEATURES Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC Low Power: 90 mW at 100 MSPS per Channel On-Chip Reference and Track/Holds 475 MHz Analog Bandwidth Each Channel SNR = 47 dB @ 41 MHz 1 V p-p Analog Input Range Each Channel Single 3.0 V Supply Operation (2.7 V to 3.6 V) Standby Mode for Single Channel Operation Two's Complement or Offset Binary Output Mode Output Data Alignment Mode Pin-Compatible 10-Bit Upgrade Available APPLICATIONS Battery-Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes I and Q Communications GENERAL DESCRIPTION
ENCA AINA AINA REFINA REFOUT REFINB AINB AINB ENCB
8-Bit, 40/80/100 MSPS Dual A/D Converter AD9288
FUNCTIONAL BLOCK DIAGRAM
VDD
OUTPUT REGISTER
TIMING
AD9288
T/H ADC 8
8
D7AD0A SELECT #1 SELECT #2
REF
OUTPUT REGISTER
DATA FORMAT SELECT 8 D7BD0B
T/H
ADC
8
TIMING
VD
GND
VDD
The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is optimized for low cost, low power, small size, and ease of use. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.
The encode input is TTL/CMOS-compatible and the 8-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options are available to offer a combination of standby modes, digital data formats and digital data timing schemes. In standby mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9288 is available in a 48-lead surface mount plastic package (7 × 7 mm, 1.4 mm LQFP) specified over the industrial temperature range (40°C to +85°C). The AD9288 is pin-compatible with the 10-bit AD9218, facilitating future system migrations.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD9288SPECIFICATIONS (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 Gain Matching Voltage Matching ANALOG INPUT Input Voltage Range (With Respect to AIN) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage
3
DD
= 3.0 V; VD = 3.0 V, Differential Input; External reference unless otherwise noted.)
Min AD9288BST-80 Typ Max 8 +1.25 1.50 +1.25 1.50 +6 +8 6 8 ± 0.5 ± 0.50 Guaranteed ± 2.5 80 ± 1.5 ± 15 +1.25 1.50 +1.25 1.50 +6 +8 6 8 Min AD9288BST-40 Typ Max 8 ± 0.5 ± 0.50 Guaranteed ± 2.5 80 ± 1.5 ± 15 +1.25 1.50 +1.25 1.50 +6 +8 Unit Bits LSB LSB LSB LSB % FS % FS ppm/°C % FS mV
Test Temp Level
Min
AD9288BST-100 Typ Max 8
25°C Full 25°C Full Full 25°C Full Full 25°C 25°C
I VI I VI VI I VI VI V V
± 0.5 ± 0.50 Guaranteed ± 2.5 80 ± 1.5 ± 15
6 8
Full Full 25°C Full Full Full 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Full Full Full Full Full Full 25°C Full Full Full Full 25°C 25°C 25°C
V V I VI VI VI I VI V V VI IV IV IV V V VI VI VI VI VI VI V VI VI VI VI I V V
0.3 × VD 0.2 35 40 1.2 7 5
± 512 0.3 × VD ± 10 1.25 ± 130 10 2 475
0.3 × VD +0.2 +35 +40 1.3 13 16
0.3 × VD 0.2 35 40 1.2 7 5
± 512 0.3 × VD 0.3 × VD +0.2 ± 10 +35 +40 1.25 1.3 ± 130 10 13 16 2 475
0.3 × VD 0.2 35 40 1.2 7 5
± 512 0.3 × VD ± 10 1.25 ± 130 10 2 475
0.3 × VD +0.2 +35 +40 1.3 13 16
mV p-p V mV mV V ppm/°C k k pF MHz MSPS MSPS ns ns ps ps rms ns ns V V µA µA pF V V mW mW mV/V ns ns
100 4.3 4.3 300 5 3.0 4.5 1 1000 1000
80 5.0 5.0 300 5 3.0 4.5 1 1000 1000
40 8.0 8.0 300 5 3.0 4.5 1 1000 1000
2
2 6.0 2.0 0.8 ±1 ±1
2 6.0 2.0 0.8 ±1 ±1
6.0
2.0
0.8 ±1 ±1 2.0 2.45
2.0 2.45 0.05 180 6 8 2 2 218 11 20 2.45
2.0
0.05 171 6 8 2 2 207 11 20 156 6 8 2 2
0.05 189 11 20
POWER SUPPLY Power Dissipation4 Standby Dissipation4, 5 Power Supply Rejection Ratio (PSRR) DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 26 MHz fIN = 41 MHz
6
25°C 25°C 25°C
I I I
44
47.5 47.5 47.0
44
47.5 47
44
47.5
dB dB dB
2
REV. B
AD9288
Parameter
6
Test Temp Level
Min
AD9288BST-100 Typ Max
Min
AD9288BST-80 Typ Max
Min
AD9288BST-40 Typ Max
Unit
DYNAMIC PERFORMANCE (Continued) Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz 2 5 °C I
47
47
44
47
dB
fIN = 26 MHz 2 5° C I 2 5° C I fIN = 41 MHz Effective Number of Bits 25° C I fIN = 10.3 MHz fIN = 26 MHz 2 5° C I 2 5° C I fIN = 41 MHz 2nd Harmonic Distortion 25° C I fIN = 10.3 MHz fIN = 26 MHz 2 5° C I 2 5° C I fIN = 41 MHz 3rd Harmonic Distortion 25° C I fIN = 10.3 MHz fIN = 26 MHz 2 5° C I 2 5° C I fIN = 41 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz 25° C V
44
47 47 7.5 7.5 7.5 70 70 70 60 60 60 60
44
47 47 7.5 7.5 7.5 70 70 70 60 60 60 60 7.0 7.5
dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc
7.0
7.0
55
70
55
55
55
60
55
52
60
NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and tPD are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 µA. 3 Digital supply current based on V DD = 3.0 V output drive with <10 pF loading under dynamic test conditions. 4 Power dissipation measured under the following conditions: f S = 100 MSPS, analog input is 0.7 dBFS, both channels in operation. 5 Standby dissipation calculated with encode clock in operation. 6 SNR/harmonics based on an analog input voltage of 0.7 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . 55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . 65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Test Level I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Table I. User Select Options
ORDERING GUIDE
S1 Model AD9288BST -40, -80, -100 AD9288/PCB Temperature Ranges 40°C to +85°C 25 °C Package Options S T - 4 8* Evaluation Board 0 0 1 1
S2 0 1 0 1
User Select Options Standby Both Channels A and B. Standby Channel B Only. Normal Operation (Data Align Disabled). Data align enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed a 1/2 clock cycle).
*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7 × 7 mm: LQFP).
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9288 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
3
AD9288
PIN CONFIGURATION
D7A (MSB)
Aperture Delay
The delay between a differential crossing of ENCODE and ENCODE and the instant at which the analog input is sampled.
D6A D5A D4A D3A D2A D1A D0A
ENCA VDD
VD
GND
Aperture Uncertainty (Jitter)
48 47 46 45 44 43 42 41 40 39 38 37
The sample-to-sample variation in aperture delay.
36 35
GND 1 AINA 2 AINA 3 DFS 4 REFINA 5 REFOUT 6 REFINB 7 S1 8 S2 9 AINB 10 AINB 11 GND 12
PIN 1 IDENTIFIER
NC NC 34 GND 33 VDD
32
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
GND
AD9288
TOP VIEW (Not to Scale)
VD VD 29 GND 28 VDD
31 30 27 26 25
GND NC NC
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic "1" state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
Integral Nonlinearity
ENCB VDD
GND
VD
D3B D2B
D1B
(MSB) D7B D6B
D5B D4B
D0B
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
PIN FUNCTION DESCRIPTIONS
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
Pin No.
Name
Description Ground Analog Input for Channel A Analog Input for Channel A (Complementary) Data Format Select: (Offset binary output available if set low. Twos complement output available if set high). Reference Voltage Input for Channel A. Internal Reference Voltage Reference Voltage Input for Channel B User Select #1 (Refer to Table I), Tied with Respect to VD User Select #2 (Refer to Table I), Tied with Respect to VD Analog Input for Channel B (Complementary) Analog Input for Channel B Analog Supply (3 V) Clock Input for Channel B Digital Supply (3 V) Digital Output for Channel B Do Not Connect Digital Output for Channel A Clock Input for Channel A
The encode rate at which parametric testing is performed.
Output Propagation Delay
1, 12, 16, 27, 29, 32, 34, 45 GND 2 AINA 3 AINA 4 DFS
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
5 6 7 8 9 10 11 13, 30, 31, 48 14 15, 28, 33, 46 1724 25, 26, 35, 36 3744 47
R E F I NA R E FOUT R E F I NB S1 S2 AINB AINB VD E N CB V DD D7BD0B NC D0AD7A ENCA
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale).
Worst Harmonic
DEFINITION OF SPECIFICATIONS Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. 4
The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc.
REV. B
AD9288
SAMPLE N SAMPLE N+1 SAMPLE N+5
A I N A, AI N B
tA tEH tEL
1/ f
S
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
ENCODE A, B
tPD
tV
D7AD0A
DATA N4
DATA N3
DATA N2
DATA N1
DATA N
DATA N+1
D7BD0B
DATA N4
DATA N3
DATA N2
DATA N1
DATA N
DATA N+1
Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE N N+1 N+2
SAMPLE N+3
SAMPLE N+4
AINA, AINB
tA tEH tEL
1/ f
S
ENCODE A ENCODE B
tPD tV
D7AD0A
DATA N8
DATA N6
DATA N4
DATA N2
DATA N
DATA N+2
D7BD0B
DATA N7
DATA N5
DATA N3
DATA N1
DATA N+1
DATA N+3
Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
REV. B
5
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