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Details, datasheet, quote on part number:AD9762s
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| Part: | AD9762s |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => 10-14 bit |
| Description: | 12-Bit, 100 MSPS+ TxDAC® D/A Converter |
| Company: | Analog Devices |
| Datasheet: | Download AD9762s datasheet File size : 424 kB |
| Request For quote: | Find where to buy AD9762s
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Datasheet text preview:
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FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 70 dBc Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 25 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Package: 28-Lead SOIC and TSSOP Edge-Triggered Latches APPLICATIONS Communication Transmit Channel: Basestations (Single/Multichannel Applications) ADSL/HFC Modems Direct Digital Synthesis (DDS) Instrumentation PRODUCT DESCRIPTION
0.1 F
12-Bit, 125 MSPS TxDAC® D/A Converter AD9762*
FUNCTIONAL BLOCK DIAGRAM
+5V 0.1 F
REFLO +1.20V REF 50pF REFIO FS ADJ RSET +5V DVDD DCOM CLOCK CLOCK SLEEP SEGMENTED SWITCHES
COMP1
AVDD
ACOM
AD9762
CURRENT SOURCE ARRAY COMP2 0.1 F
IOUTA LSB SWITCHES IOUTB
LATCHES
DIGITAL DATA INPUTS (DB11DB0)
The AD9762 is the 12-bit resolution member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The AD9762 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9762's flexible single-supply operating range of 2.7 V to 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 45 mW without a significant degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 25 mW. The AD9762 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families. The AD9762 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 k output impedance.
TxDAC is a registered trademark of Analog Devices, Inc. *Patent pending.
Differential current outputs are provided to support singleended or differential applications. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V. The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9762 can be driven by the on-chip reference or by a variety of external reference voltages. The internal control amplifier which provides a wide (>10:1) adjustment span allows the AD9762 full-scale current to be adjusted over a 2 mA to 20 mA range while maintaining excellent dynamic performance. Thus, the AD9762 may operate at reduced power levels or be adjusted over a 20 dB range to provide additional gain ranging capabilities. The AD9762 is available in 28-lead SOIC and TSSOP packages. It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
1. The AD9762 is a member of the TxDAC product family which provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. Manufactured on a CMOS process, the AD9762 uses a proprietary switching technique that enhances dynamic performance beyond what was previously attainable by higher power/cost bipolar or BiCMOS devices. 3. On-chip, edge-triggered input CMOS latches interface readily to +3 V and +5 V CMOS logic families. The AD9762 can support update rates up to 125 MSPS. 4. A flexible single-supply operating range of 2.7 V to 5.5 V and a wide full-scale current adjustment span of 2 mA to 20 mA allow the AD9762 to operate at reduced power levels. 5. The current output(s) of the AD9762 can be easily configured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD9762SPECIFICATIONS
DC SPECIFICATIONS (T
Parameter RESOLUTION DC ACCURACY1 Integral Linearity Error (INL) TA = +25°C TMIN to TMAX Differential Nonlinearity (DNL) TA = +25°C TMIN to TMAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth (w/o CCOMP1)4 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages A V D D5 DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)6 Supply Current Sleep Mode (IAVDD) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Dissipation7 (5 V, IOUTFS = 20 mA) Power Dissipation7 (3 V, IOUTFS = 2 mA) Power Supply Rejection Ratio--AVDD Power Supply Rejection Ratio--DVDD OPERATING RANGE
MIN
to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Min 12 Typ Max Units Bits
2.5 4.0 1.5 2.0 0.025 10 10 2.0 1.0
± 0.75 ± 1.0 ± 0.5 ± 0.75
+2.5 +4.0 +1.5 +2.0 +0.025 +10 +10 20.0 +1.25
LSB LSB LSB LSB % of FSR % of FSR % of FSR mA V k pF V nA V M MHz ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C p p m /° C
±2 ±1 100 5
1.08
1.20 100
1.32
0.1 1 1.4 0 ± 50 ± 100 ± 50
1.25
2.7 2.7
5.0 5.0 25 1.5 133 190 45
5.5 5.5 30 2 8.5 160
0.4 0.025 40
+0.4 +0.025 +85
V V mA mA mA mW mW mW % of FSR/V % of FSR/V °C
NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 × the IREF current. 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz. 7 Measured as unbuffered voltage output into 50 RLOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and f OUT = 40 MHz. Specifications subject to change without notice.
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AD9762 DYNAMIC SPECIFICATIONS 50
Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA) AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz TA = +25°C TMIN to TMAX fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.51 MHz fCLOCK = 50 MSPS; fOUT = 5.02 MHz fCLOCK = 50 MSPS; fOUT = 20.2 MHz fCLOCK = 100 MSPS; fOUT = 2.51 MHz fCLOCK = 100 MSPS; fOUT = 5.04 MHz fCLOCK = 100 MSPS; fOUT = 20.2 MHz fCLOCK = 100 MSPS; fOUT = 40.4 MHz Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT =1.00 MHz; 2 MHz Span TA = +25°C TMIN to TMAX fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz TA = +25°C TMIN to TMAX fCLOCK = 50 MHz; fOUT = 2.00 MHz fCLOCK = 100 MHz; fOUT = 2.00 MHz Multitone Power Ratio (8 Tones at 110 kHz Spacing) fCLOCK = 20 MSPS; fOUT = 2.00 MHz to 2.99 MHz
NOTES 1 Measured single ended into 50 load. Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, Doubly Terminated, unless otherwise noted)
Min 125 35 1 5 2.5 2.5 50 30 Typ Max Units MSPS ns ns pV-s ns ns pA/Hz pA/Hz
75 73
79 79 74 70 57 73 67 57 53
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
78 76
86 84 84
dBc dBc dBc dBc
78 75 75 73
74 72
dBc dBc dBc dBc dBc
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AD9762 DIGITAL SPECIFICATIONS (T
Parameter DIGITAL INPUTS Logic "1" Voltage @ DVDD = +5 V Logic "1" Voltage @ DVDD = +3 V Logic "0" Voltage @ DVDD = +5 V Logic "0" Voltage @ DVDD = +3 V Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW)
Specifications subject to change without notice.
MIN
to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
Min 3.5 2.1 Typ 5 3 0 0 Max Units V V V V µA µA pF ns ns ns
10 10 5 2.0 1.5 3.5
1.3 0.9 +10 +10
DB0DB11
tS
CLOCK
tH tLPW tPD tST
0.1% 0.1%
IOUTA OR IOUTB
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, IOUTB COMP1, COMP2 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM ACOM Min 0.3 0.3 0.3 6.5 0.3 0.3 1.0 0.3 0.3 0.3 65 Max +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 +300 Units V V V V V V V V V V °C °C °C
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option*
AD9762AR 40°C to +85°C 28-Lead 300 mil SOIC R-28 AD9762ARU 40°C to +85°C 28-Lead TSSOP RU-28 AD9762-EB Evaluation Board
*R = SOIC, RU = TSSOP.
THERMAL CHARACTERISTICS Thermal Resistance
28-Lead 300 mil SOIC JA = 71.4°C/W JC = 23°C/W 28-Lead TSSOP JA = 97.9°C/W JC = 14.0°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9762 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9762
PIN CONFIGURATION
(MSB) DB11 1 DB10 2 DB9 3 DB8 4 DB7 5 DB6 6 28 CLOCK 27 DVDD 26 DCOM 25 NC
AD9762
24 AVDD
TOP VIEW 23 COMP2 DB5 7 (Not to Scale) 22 IOUTA DB4 8 DB3 9 DB2 10 DB1 11 DB0 12 NC 13 NC 14 21 IOUTB 20 ACOM 19 COMP1 18 FS ADJ 17 REFIO 16 REFLO 15 SLEEP
NC = NO CONNECT
PIN DESCRIPTIONS
Pin No. 1 211 12 13, 14, 25 15 16 17
Name DB11 DB10DB1 DB0 NC SLEEP REFLO REFIO
Description Most Significant Data Bit (MSB). Data Bits 110. Least Significant Data Bit (LSB). No Internal Connection. Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. Analog Supply Voltage (+2.7 V to +5.5 V). Digital Common. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input. Data latched on positive edge of clock.
18 19 20 21 22 23 24 26 27 28
FS ADJ COMP1 ACOM IOUTB IOUTA COMP2 AVDD DCOM DVDD CLOCK
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