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Details, datasheet, quote on part number:AD9763
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| Part: | AD9763 |
| Category: | Data Conversion => DAC (Digital to Analog Converters) => 10-14 bit |
| Description: | 10-Bit, 125 MSPS Dual TxDAC+® |
| Company: | Analog Devices |
| Datasheet: | Download AD9763 datasheet File size : 476 kB |
| Request For quote: | Find where to buy AD9763
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Datasheet text preview:
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FEATURES 10-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 mHz Output: 75 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation Power Dissipation: 380 mW @ 5 V Power-Down Mode: 50 mW @ 5 V 48-Lead LQFP APPLICATIONS Communications Base Stations Digital Synthesis Quadrature Modulation PRODUCT DESCRIPTION
10-Bit, 125 MSPS Dual TxDAC+® D/A Converter AD9763*
FUNCTIONAL BLOCK DIAGRAM
DVDD DCOM AVDD ACOM CLK1 "1" DAC IOUTA1 IOUTB1 REFIO FSADJ1 FSADJ2 GAINCTRL SLEEP IOUTA2 IOUTB2 PORT1 "1" LATCH
WRT1 WRT2
REFERENCE DIGITAL INTERFACE
AD9763
BIAS GENERATOR
PORT2
"2" LATCH MODE
"2" DAC CLK2
The AD9763 is a dual port, high-speed, two-channel, 10-bit CMOS DAC. It integrates two high quality 10-bit TxDAC+ cores, a voltage reference and digital interface circuitry into a small 48-lead LQFP package. The AD9763 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9763 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9763 to interface to two separate data ports, or to a single interleaved high-speed data port. In interleaving mode the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor.** The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or differential applications. Both DACs can be simultaneously updated and provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%. The AD9763 is manufactured on an advanced low cost CMOS process. It operates from a single supply of 3.0 V to 5.0 V and consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9763 is a member of a pin-compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution. 2. Dual 10-Bit, 125 MSPS DACs: A pair of high performance DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 3. Matching: Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. Low Power: Complete CMOS Dual DAC function operates on 380 mW from a 3.0 V to 5.0 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference: The AD9763 includes a 1.20 V temperature-compensated bandgap voltage reference. 6. Dual 10-Bit Inputs: The AD9763 features a flexible dualport interface allowing dual or interleaved input data.
TxDAC+ is a registered trademark of Analog Devices, Inc. * Patent pending. ** Please see GAINCTRL Mode section, for important date code information on this feature.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD9763SPECIFICATIONS
DC SPECIFICATIONS (T
Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) Differential Linearity Error (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Gain Match Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Digital Supply Current (IDVDD)5 Supply Current Sleep Mode (IAVDD) Power Dissipation4 (5 V, IOUTFS = 20 mA) Power Dissipation5 (5 V, IOUTFS = 20 mA) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Supply Rejection Ratio7--AVDD Power Supply Rejection Ratio7--DVDD OPERATING RANGE
1
MIN
to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, unless otherwise noted.)
Min 10 1 0.5 0.02 2 5 1.6 0.14 2.0 1.0 ± 0.1 ± 0.07 +1 +0.5 +0.02 +2 +5 +1.6 +0.14 20.0 +1.25 Typ Max Unit Bits LSB LSB % of FSR % of FSR % of FSR % of FSR dB mA V k pF V nA V M MHz ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C p p m /° C
± 0.25 ±1 0.1
100 5 1.14 1.20 100 1.26
0.1 1 0.5 0 ± 50 ± 100 ± 50
1.25
3 2.7
5 5 71 5 8 380 420 450
5.5 5.5 75 7 15 12.0 410 450 +0.4 +0.025 +85
0.4 0.025 40
V V mA mA mA mA mW mW mW % of FSR/V % of FSR/V °C
NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz. 5 Measured at fCLOCK = 100 MSPS and f OUT = 1 MHz. 6 Measured as unbuffered voltage output with I OUTFS = 20 mA and 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and f OUT = 40 MHz. 7 ± 10% Power supply variation. Specifications subject to change without notice.
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AD9763 DYNAMIC SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (90% to 10%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA) AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 100 MSPS; fOUT = 1.00 MHz 0 dBFS Output 6 dBFS Output 12 dBFS Output 18 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 5.02 MHz fCLOCK = 65 MSPS; fOUT = 14.02 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 125 MSPS; fOUT = 25 MHz fCLOCK = 125 MSPS; fOUT = 40 MHz Spurious-Free Dynamic Range Within a Window fCLOCK = 100 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 10 MHz Span fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 10 MHz Span fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 10 MHz Span Total Harmonic Distortion fCLOCK = 100 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 4.00 MHz fCLOCK = 125 MSPS; fOUT = 10.00 MHz Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLOCK = 65 MSPS; fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output 6 dBFS Output 12 dBFS Output 18 dBFS Output Channel Isolation fCLOCK = 125 MSPS; fOUT = 10 MHz fCLOCK = 125 MSPS; fOUT = 40 MHz
NOTES 1 Measured single-ended into 50 load. Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted.)
Min 125 35 1 5 2.5 2.5 50 30 Typ Max Unit MSPS ns ns pV-s ns ns pA/ Hz pA/ Hz
69
78 74 69 61 79 78 75 66 55 67 60 85 80 82 82 77 77 74 72 69
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
78
76 74 71 67 85 77
dBc dBc dBc dBc dBc dBc
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AD9763SPECIFICATIONS
DIGITAL SPECIFICATIONS (T
Parameter DIGITAL INPUTS Logic "1" Voltage @ DVDD = 5 V Logic "1" @ DVDD = 3 Logic "0" Voltage @ DVDD = 5 V Logic "0" @ DVDD = 3 Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW, tCPW)
Specifications subject to change without notice.
MIN
to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, unless otherwise noted.)
Min 3.5 2.1 0 10 10 5 2.0 1.5 3.5 Typ 5 3 0 Max Unit V V V V µA µA pF ns ns ns
1.3 0.9 +10 +10
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD DVDD ACOM AVDD MODE, CLK1, CLK2, WRT1, WRT2 Digital Inputs I O U T A 1 / I O U T A 2 , I O U T B 1/ I O U T B 2 REFIO, FSADJ1, FSADJ2 GAINCTRL, SLEEP Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect to ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM
Min 0.3 0.3 0.3 6.5 0.3 0.3 1.0 0.3 0.3 65
Max +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300
Unit V V V V V V V V V °C °C °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
tS tH
Model AD9763AST AD9763-EB
Temperature Range 40°C to +85°C
Package Description
Package Option*
DATA IN
48-Lead LQFP ST-48 Evaluation Board
(WRT2) (WRT1 / IQWRT) (CLK2) (CLK1/ IQCLK)
t LPW t CPW
*ST = Thin Plastic Quad Flatpack.
THERMAL CHARACTERISTICS Thermal Resistance
IOUTA OR IOUTB
t PD
48-Lead LQFP JA = 91°C/W
Figure 1. Timing Diagram for Dual and Interleaved Modes
See Dynamic and Digital sections for timing specifications.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9763 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9763
PIN FUNCTION DESCRIPTIONS
Pin No. 110 1114, 3336 15, 21 16, 22 17 18 19 20 2332 37 38 39, 40 41 42 43 44 45, 46 47 48
Name PORT1 NC DCOM1, DCOM2 DVDD1, DVDD2 WRT1/IQWRT CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL PORT2 SLEEP ACOM IOUTA2, IOUTB2 FSADJ2 GAINCTRL REFIO FSADJ1 I O U T B 1, I O U T A 1 AVDD MODE
Description Data Bits DB9P1 to DB0P1. No Connection Digital Common Digital Supply Voltage Input write signal for PORT 1 (IQWRT in interleaving mode). Clock input for DAC1 (IQCLK in interleaving mode). Clock input for DAC2 (IQRESET in interleaving mode). Input write signal for PORT 2 (IQSEL in interleaving mode). Data Bits DB9P2 to DB0P2. Power-Down Control Input Analog Common "PORT 2" differential DAC current outputs. Full-scale current output adjust for DAC2. GAINCTRL Mode (0 = 2 resistor, 1 = 1 resistor). Reference Input/Output Full-scale current output adjust for DAC1. "PORT 1" differential DAC current outputs. Analog Supply Voltage Mode Select (1 = Dual Port, 0 = Interleaved).
PIN CONFIGURATION
GAINCTRL
FSADJ1
FSADJ2
48 47 46 45 44 43 42 41 40 39 38 37
DB9P1 (MSB) 1 DB8P1 2 DB7P1 3 DB6P1 4 DB5P1 5 DB4P1 6 DB3P1 7 DB2P1 8 DB1P1 9 DB0P1 10 NC 11 NC 12
SLEEP
36 NC 35 NC 34 NC 33 NC 32 DB0P2 31 DB1P2 30 DB2P2 29 DB3P2 28 DB4P2 27 DB5P2 26 DB6P2 25 DB7P2
IOUTA1
IOUTB1
IOUTB2
IOUTA2 DVDD2
REFIO
PIN 1 IDENTIFIER
AD9763
TOP VIEW (Not to Scale)
13 14 15 16 17 18 19 20 21 22 23 24
ACOM DB9-P2 (MSB)
MODE
AVDD
WRT1/ IQWRT
CLK1/ IQCLK
NC = NO CONNECT
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5
CLK2/ IQRESET
WRT2/ IQSEL
DB8P2
NC
NC
DCOM1
DVDD1
DCOM2
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