|
Details, datasheet, quote on part number:AD9854
| |
Datasheet text preview:
a
FEATURES 300 MHz Internal Clock Rate FSK, BPSK, PSK, CHIRP, AM Operation Dual Integrated 12-Bit D/A Converters Ultrahigh-Speed Comparator, 3 ps RMS Jitter Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz ( 1 MHz) AOUT 4 to 20 Programmable Reference Clock Multiplier Dual 48-Bit Programmable Frequency Registers Dual 14-Bit Programmable Phase Offset Registers 12-Bit Amplitude Modulation and Programmable Shaped On/Off Keying Function Single Pin FSK and BPSK Data Interface PSK Capability Via I/O Interface Linear or Nonlinear FM Chirp Functions with Single Pin Frequency "Hold" Function Frequency-Ramped FSK <25 ps RMS Total Jitter in Clock Generator Mode Automatic Bidirectional Frequency Sweeping SIN(x)/x Correction Simplified Control Interface 10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible or 100 MHz Parallel 8-Bit Programming 3.3 V Single Supply
CMOS 300 MSPS Quadrature Complete-DDS AD9854
Multiple Power-Down Functions Single-Ended or Differential Input Reference Clock Small 80-Lead LQFP Packaging APPLICATIONS Agile, Quadrature L.O. Frequency Synthesis Programmable Clock Generator FM Chirp Source for Radar and Scanning Systems Test and Measurement Equipment Commercial and Amateur RF Exciter GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high-speed, high-performance quadrature D/A converters to form a digitally programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase amplitude-programmable sine and cosine outputs that can be used as an agile L.O. in communications, radar, and many other applications. The AD9854's innovative high-speed DDS core provides 48-bit frequency r e s o l u t i o n (1 microHertz tuning resolution with 300 M H z SYSCLK). Maintaining 17 bits assures excellent SFDR. The AD9854's circuit architecture allows the generation of
(continued on page 14)
FUNCTIONAL BLOCK DIAGRAM
SYSTEM CLOCK
FREQUENCY ACCUMULATOR ACC 1 PHASE ACCUMULATOR ACC 2
PHASE-TOAMPLITUDE CONVERTER
REFERENCE CLOCK IN
REF CLK BUFFER
4 20 REF CLK MULTIPLIER
DDS CORE
I 12 17 17
DIGITAL MULTIPLIERS INV. SINC FILTER
MUX MUX
12
12-BIT "I" DAC
ANALOG OUT DAC RSET ANALOG OUT
48
48
DIFF/SINGLE SELECT
MUX SYSTEM CLOCK D E M U X 3 DELTA FREQUENCY RATE TIMER 2 48 SYSTEM CLOCK
SYSTEM CLOCK INV. SINC FILTER 12-BIT "Q" DAC OR CONTROL 12 DAC
MUX MUX
48
14
Q 12
FSK/BPSK/HOLD DATA IN
MUX
MUX
MUX SYSTEM CLOCK
12
12
PROGRAMMABLE AMPLITUDE AND RATE CONTROL COMPARATOR
ANALOG IN
48
FREQUENCY TUNING WORD 1
48
14
14
2ND 14-BIT PHASE/ OFFSET WORD
12
12 CLOCK OUT SHAPED ON/OFF KEYING BUS GND +VS
DELTA FREQUENCY WORD MODE SELECT
FREQUENCY 1ST 14-BIT PHASE/ TUNING OFFSET WORD WORD 2
12-BIT DC I AND Q 12-BIT AM MODULATION CONTROL
PROGRAMMING REGISTERS
2 SYSTEM CLOCK
SYSTEM CLOCK BIDIRECTIONAL INTERNAL/EXTERNAL I/O UPDATE CLOCK INT
CK Q D
AD9854
EXT
INTERNAL PROGRAMMABLE UPDATE CLOCK
I/O PORT BUFFERS
READ
WRITE
SERIAL/ PARALLEL SELECT
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
6-BIT ADDRESS OR SERIAL PROGRAMMING LINES
8-BIT PARALLEL LOAD
MASTER RESET
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD9854
TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . 5 Test Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TYPICAL APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . 12 O V E R V I E W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DESCRIPTION OF AD9854 MODES OF OPERATION . . 14 Single-Tone (Mode 000) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Unramped FSK (Mode 001) . . . . . . . . . . . . . . . . . . . . . . 15 Ramped FSK (Mode 010) . . . . . . . . . . . . . . . . . . . . . . . . 15 Chirp (Mode 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Basic FM Chirp Programming Steps . . . . . . . . . . . . . . . . 19 BPSK (Mode 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 USING THE AD9854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Internal and External Update Clock . . . . . . . . . . . . . . . . . 21 Shaped On/Off Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I and Q DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Control DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Inverse SINC Function . . . . . . . . . . . . . . . . . . . . . . . . . . 23 REFCLK Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PROGRAMMING THE AD9854 . . . . . . . . . . . . . . . . . . . 24 Parallel I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial Port I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . 26 GENERAL OPERATION OF THE SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial Interface Port Pin Description . . . . . . . . . . . . . . . . 27 Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . . 27 MSB/LSB TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Control Register Description . . . . . . . . . . . . . . . . . . . . . . 28 POWER DISSIPATION AND THERMAL CONSIDERATIONS . . . . . . . . . . . . . . . . . 29 THERMAL IMPEDANCE . . . . . . . . . . . . . . . . . . . . . . . . . 30 JUNCTION TEMPERATURE CONSIDERATIONS . . . . 30 EVALUATION OF OPERATING CONDITIONS . . . . . . 31 THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES . . . . . . . . . . . . . . . . . . . . 31 EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . 32 EVALUATION BOARD INSTRUCTIONS . . . . . . . . . . . 32 I n t r o d u c t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 GENERAL OPERATING INSTRUCTIONS . . . . . . . . . . 32 Attach REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Clock Input, J25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Three-State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 P r o g r a m m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low-Pass Filter Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Observing the Unfiltered IOUT1 and the Unfiltered IOUT2 DAC Signals . . . . . . . . . . . . . . . . . . . 33 Observing the Filtered IOUT1 and the Filtered IOUT2 . . . . 33 Observing the Filtered IOUT and the Filtered IOUTB . . . . . 33 To Connect the High-Speed Comparator . . . . . . . . . . . . 34 Single-Ended Configuration . . . . . . . . . . . . . . . . . . . . . . . 34 USING THE PROVIDED SOFTWARE . . . . . . . . . . . . . . 34 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 41 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
REV. B
AD9854
(VS = 3.3 V 5%, RSET = 3.9 k external reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10 for AD9854ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 10 for AD9854AST unless otherwise noted.)
Parameter REF CLOCK INPUT CHARACTERISTICS Internal System Clock Frequency Range REFCLK Multiplier Enabled REFCLK Multiplier Disabled External REF Clock Frequency Range REFCLK Multiplier Enabled REFCLK Multiplier Disabled Duty Cycle Input Capacitance Input Impedance Differential Mode Common-Mode Voltage Range Minimum Signal Amplitude2 Common-Mode Range VIH (Single-Ended Mode) VIL (Single-Ended Mode) DAC STATIC OUTPUT CHARACTERISTICS Output Update Speed Resolution I and Q Full-Scale Output Current I and Q DAC DC Gain Imbalance3 Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Impedance Voltage Compliance Range DAC DYNAMIC OUTPUT CHARACTERISTICS I and Q DAC Quad. Phase Error DAC Wideband SFDR 1 MHz to 20 MHz AOUT 20 MHz to 40 MHz AOUT 40 MHz to 60 MHz AOUT 60 MHz to 80 MHz AOUT 80 MHz to 100 MHz AOUT 100 MHz to 120 MHz AOUT DAC Narrowband SFDR 10 MHz AOUT (± 1 MHz) 10 MHz AOUT (± 250 kHz) 10 MHz AOUT (± 50 kHz) 41 MHz AOUT (± 1 MHz) 41 MHz AOUT (± 250 kHz) 41 MHz AOUT (± 50 kHz) 119 MHz AOUT (± 1 MHz) 119 MHz AOUT (± 250 kHz) 119 MHz AOUT (± 50 kHz) Residual Phase Noise (AOUT = 5 MHz, Ext. CLK = 30 MHz, REFCLK Multiplier Engaged at 10×) 1 kHz Offset 10 kHz Offset 100 kHz Offset (AOUT = 5 MHz, Ext. CLK = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 10 kHz Offset 100 kHz Offset
1
SPECIFICATIONS
Temp
Test Level
Min
AD9854ASQ Typ Max
Min
AD9854AST Typ Max
Unit
Full Full Full Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C
VI VI VI VI IV IV IV IV IV IV IV I IV IV I I I I I IV I IV V V V V V V V V V V V V V V V
20 DC 5 DC 45
300 300 75 300 55
20 DC 5 DC 45
200 200 50 200 55
MHz MHz MHz MHz % pF k mV p-p V V V MSPS Bits mA dB % FS µA LSB LSB k V Degrees dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
50 3 100
50 3 100
800 1.6 2.3
1.75
1.9 1 300
800 1.6 2.3
1.75
1.9 1 200
5 0.5 6
12 10 +0.15
0.3 0.6 100 0.5 0.2 58 56 52 48 48 48 83 83 91 82 84 89 71 77 83
20 +0.5 +2.25 2 1.25 1.66 +1.0 1
5 0.5 6
12 10 +0.15
0.3 0.6 100 0.5 0.2 58 56 52 48 48
20 +0.5 +2.25 2 1.25 1.66 +1.0 1
83 83 91 82 84 89
2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C
V V V
140 138 142
140 138 142
dBc/Hz dBc/Hz dBc/Hz
V V V
142 148 152
142 148 152
dBc/Hz dBc/Hz dBc/Hz
REV. B
3
AD9854SPECIFICATIONS
Parameter Pipeline Delays4, 5, 6 DDS Core (Phase Accumulator and Phase to Amp Converter) Frequency Accumulator Inverse Sinc Filter Digital Multiplier DAC I/O Update Clock (INT MODE) I/O Update Clock (EXT MODE) MASTER RESET DURATION COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Hysteresis COMPARATOR OUTPUT CHARACTERISTICS Logic "1" Voltage, High Z Load Logic "0" Voltage, High Z Load Output Power, 50 Load, 120 MHz Toggle Rate Propagation Delay Output Duty Cycle Error7 Rise/Fall Time, 5 pF Load Toggle Rate, High Z Load Toggle Rate, 50 Load Output Cycle-to-Cycle Jitter8 COMPARATOR NARROWBAND SFDR9 10 MHz (± 1 MHz) 10 MHz (± 250 kHz) 10 MHz (± 50 kHz) 41 MHz (± 1 MHz) 41 MHz (± 250 kHz) 41 MHz (± 50 kHz) 119 MHz (± 1 MHz) 119 MHz (± 250 kHz) 119 MHz (± 50 kHz) CLOCK GENERATOR OUTPUT JITTER9 5 MHz AOUT 40 MHz AOUT 100 MHz AOUT PARALLEL I/O TIMING CHARACTERISTICS TASU (Address Setup Time to WR Signal Active) TADHW (Address Hold Time to WR Signal Inactive) TDSU (Data Setup Time to WR Signal Inactive) TDHD (Data Hold Time to WR Signal Inactive) TWRLOW (WR Signal Minimum Low Time) TWRHIGH (WR Signal Minimum High Time) TWR (Minimum Write Time) TADV (Address to Data Valid Time) TADHR (Address Hold Time to RD Signal Inactive) TRDLOV (RD Low-to-Output Valid) TRDHOZ (RD High-to-Data Three-State) SERIAL I/O TIMING CHARACTERISTICS TPRE (CS Setup Time) TSCLK (Period of Serial Data Clock) TDSU (Serial Data Setup Time) TSCLKPWH (Serial Data Clock Pulsewidth High) TSCLKPWL (Serial Data Clock Pulsewidth Low) TDHLD (Serial Data Hold Time) TDV (Data Valid Time) Temp 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV IV V IV I IV VI VI I IV I V IV IV IV V V V V V V V V V V V V IV IV IV IV IV IV IV V IV IV IV IV IV IV IV IV IV V 8.0 0 3.0 0 2.5 7 10.5 15 5 3.1 0.16 9 10 300 375 11 3 ±1 2 350 400 9 +10 10 300 375 4.0 84 84 92 76 82 89 73 73 83 23 12 7 7.5 1.6 1.8 8.0 0 3.0 0 2.5 7 10.5 15 5 84 84 92 76 82 89 11 3 ±1 2 350 400 10 3 500 ±1 10 Min AD9854ASQ Typ Max 33 26 16 9 1 2 3 10 3 500 ±1 10 3.1 0.16 Min AD9854AST Typ Max 33 26 16 9 1 2 3 Unit SysClk Cycles SysClk SysClk SysClk SysClk SysClk SysClk Cycles Cycles Cycles Cycles Cycles Cycles
SysClk Cycles pF k µA mV p-p V V dBm ns % ns MHz MHz ps rms dBc dBc dBc dBc dBc dBc dBc dBc dBc ps rms ps rms ps rms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
±5 20
±5 20
+10
4.0
23 12 7 7.5 1.6 1.8
15 15 10
15 15 10
30 100 30 40 40 0 30
30 100 30 40 40 0 30
4
REV. B
AD9854
Parameter CMOS LOGIC INPUTS10 Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance POWER SUPPLY +VS Current12 +VS Current13 +VS Current14 PDISS 12 PDISS 13 PDISS 14 PDISS Power-Down Mode
11
Temp 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C 2 5 °C
Test Level I I IV IV V I I I I I I I
Min 2.2
AD9854ASQ Typ Max
Min 2.2
AD9854AST Typ Max
Unit V V µA µA pF mA mA mA W W W mW
0.8 ±5 ±5 3 1050 710 600 3.475 2.345 1.975 1 1210 816 685 4.190 2.825 2.375 50 3 755 515 435 2.490 1.700 1.435 1
0.8 ± 12 ± 12
865 585 495 3.000 2.025 1.715 50
NOTES 1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied V DD or a 3 V TTL-level pulse input. 2 An internal 800 mV p-p differential voltage swing equates to 400 mV p-p applied to both REFCLK input pins. 3 The I and Q gain imbalance is digitally adjustable to less than 0.01 dB. 4 Pipeline delays of each individual block are fixed; however, if the 8 top MSBS of a tuning word are all zeros, the delay will appear longer. This is due to insufficient phase accumulation per a system CLK period to produce enough LSB amplitude to the D/A converter. 5 If a feature like the Inverse Sinc, which has 16 Pipeline delays, can be bypassed, the total delay will be reduced by that amount. 6 The I/O Update CLK transfers data from the I/O Port Buffers to the Programming Registers. This transfer takes system clocks to perform. 7 Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold. 8 Represents comparator's inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS 2075. 9 Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 . 10 Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 1.) 11 Simultaneous operation at the maximum ambient temperature of 85 °C and the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or 300 MHz for the thermally enhanced 80-lead LQFP may cause the maximum die junction temperature of 150 °C to be exceeded. Refer to the Power Dissipation section and Thermal Considerations for derating and thermal management information. 12 All functions engaged. 13 All functions except inverse sinc engaged. 14 ABSOLUTE MAXIMUM RATINGS* All functions except inverse sinc and digital multipliers engaged. Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS Test Level
I 100% Production Tested. III Sample Tested Only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial operating temperature range.
VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . 40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C Maximum Clock Frequency (ASQ) . . . . . . . . . . . . . 300 MHz Maximum Clock Frequency (AST) . . . . . . . . . . . . . 200 MHz JA (ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16°C/W JA (AST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38°C/W JC (ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2°C/W
*Absolute Maximum Ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
ORDERING GUIDE
Model AD9854ASQ AD9854AST AD9854/PCB
Temperature Range 40°C to +85°C 40°C to +85°C 0°C to 70°C
Package Description Thermally Enhanced 80-Lead LQFP 80-Lead LQFP Evaluation Board
Package Option SQ-80 ST-80
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9854 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
5
|
|
