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Details, datasheet, quote on part number:AD9856/PCB
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Datasheet text preview:
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FEATURES Universal Low Cost Modulator Solution for C ommunications Applications DC to 80 MHz Output Bandwidth Integrated 12-Bit D/A Converter Programmable Sample Rate Interpolation Filter Programmable Reference Clock Multiplier Internal SIN(x)/x Compensation Filter >52 dB SFDR @ 40 MHz AOUT >48 dB SFDR @ 70 MHz AOUT >80 dB Narrowband SFDR @ 70 MHz A OUT +3 V Single Supply Operation Space-Saving Surface-Mount Packaging Bidirectional Control Bus Interface Supports Burst and Continuous Tx Modes Single Tone Mode for Frequency Synthesis Applications Four Programmable, Pin-Selectable Modulator Profiles Direct Interface to AD8320/AD8321 PGA Cable Driver
CMOS 200 MHz Quadrature Digital Upconverter AD9856
APPLICATIONS HFC Data, Telephony and Video Modems Wireless and Satellite Communications Cellular Basestations GENERAL DESCRIPTION
The AD9856 integrates a high speed direct-digital synthesizer (DDS), a high performance, high speed 12-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters and other DSP functions onto a single chip, to form a complete quadrature digital upconverter device. The AD9856 is intended to function as a universal I/Q modulator and agile upconverter for communications applications, where cost, size, power dissipation and dynamic performance are critical attributes. The AD9856 is available in a space-saving surface mount package and specified to operate over the extended industrial temperature range of 40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DEMULTIPLEXER AND SERIAL-TO-PARALLEL CONVERTER
12
4 8 SELECTABLE INTERPOLATING HALFBANDS 4 8 SELECTABLE INTERPOLATING HALFBANDS 4 20 PROG. CLOCK MULTIPLIER
12
2 TO 63 SELECTABLE INTERPOLATOR
12
12 12
AD9856
INV 12 SINC 12-BIT DAC DC-80 MHz OUTPUT DAC RSET SPI INTERFACE TO AD8320/AD8321 PROGRAMMABLE CABLE DRIVER AMPLIFIER
COMPLEX DATA IN
12
12
2 TO 63 SELECTABLE INTERPOLATOR
12 12 SINE
12 12 COSINE
TxENABLE (I / Q SYNC)
DDS AND CONTROL FUNCTIONS
REFERENCE CLOCK IN
PROFILE SELECT 12
PROFILE SELECT 34
MASTER RESET
BIDIRECTIONAL SPI CONTROL INTERFACE: 32-BIT FREQUENCY TUNING WORD FREQUENCY UPDATE INTERPOLATION FILTER RATE REFERENCE CLOCK MULTIPLIER RATE SPECTRAL PHASE INVERSION ENABLE CABLE DRIVER AMPLIFIER CONTROL
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9856SPECIFICATIONS with REFCLK Multiplier enabled at 20
Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4× REFCLK Multiplier Enabled at 20× Duty Cycle Input Capacitance Input Impedance DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Phase Noise @ 1 kHz Offset, 40 MHz AOUT REFCLK Multiplier Enabled at 20× REFCLK Multiplier at 4× REFCLK Multiplier Disabled Voltage Compliance Range Wideband SFDR: 1 MHz Analog Out 20 MHz Analog Out 42 MHz Analog Out 65 MHz Analog Out 80 MHz Analog Out Narrowband SFDR: (± 100 kHz Window) 70 MHz Analog Out MODULATOR CHARACTERISTICS Adjacent Channel Power (CH Power = 6.98 dBm) Error Vector Magnitude I/Q Offset Inband Spurious Emissions Pass Band Amplitude Ripple (DC to 80 MHz) TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulsewidth High (tPWH) Minimum Clock Pulsewidth Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS ) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Wake-Up Time2 Minimum RESET Pulsewidth High (tRH) CMOS LOGIC INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Temp Test Level
(VS = +3 V
5%, RSET = 3.9 k , External reference clock frequency = 10 MHz ).
AD9856 Typ
Min
Max
Units
Full Full Full +25°C +25°C +25°C
VI VI VI V V V
5 5 5 50 3 100 12 10
200 1 50 10
MHz MHz MHz % pF M Bits mA %FS µA LSB LSB pF dBc/Hz dBc/Hz dBc/Hz V dBc dBc dBc dBc dBc dBc dBm % dB dBc dB
+25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C
I I V V V V V V I IV IV IV IV IV IV IV IV IV IV V
5 10
20 +10 10
0.5 1 5 85 100 110 0.5 70 65 60 55 50 80 50 50 45 1 55 50 ± 0.3 2 1.5
Full Full Full Full Full Full Full Full Full
IV IV IV IV IV IV IV IV IV
10 30 30 1 25 0 30 1 5
MHz ns ns ms ns ns ns ms REFCLK Cycles V V µA µA pF
+25°C +25°C +25°C +25°C +25°C
I I I I V
+2.6 +0.4 12 12 3
2
REV. B
AD9856
Parameter CMOS LOGIC OUTPUTS (1 mA LOAD) Logic "1" Voltage Logic "0" Voltage POWER SUPPLY +VS Current Full Operating Conditions2 Burst Operation (25%) Single Tone Mode 160 MHz Clock 120 MHz Clock Power-Down Mode Temp +25°C +25°C Test Level I I Min 2.7 0.4 AD9856 Typ Max Units mA mA
+25°C +25°C +25°C +25°C +25°C +25°C
I I I I I I
530 450 495 445 345 2
mA mA mA mA mA mA
NOTES 1 For 200 MHz operation in Modulation Mode at +85 °C operating temperature, V S must be +3 V min. 2 Assuming 1.3 k and 0.01 µF loop filter components. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Maximum Junction Temperature . . . . . . . . . . . . . . . .+165°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C V S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V Operating Temperature . . . . . . . . . . . . . . . . . 40°C to +85°C Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 V to +VS Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . .+300°C Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 38°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
Test Level I III IV V VI 100% Production Tested. Sample Tested Only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. Devices are 100% production tested at +25°C and guaranteed by design and characterization testing for industrial operating temperature range.
ORDERING GUIDE Temperature Range Package Description Package Option
Model AD9856AST AD9856/PCB
40°C to +85°C Thin Quad Flatpack ST-48 + 2 5° C Evaluation Board
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9856 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
3
AD9856
PIN FUNCTION DESCRIPTIONS
Pin # 1 2 3 4, 10, 21, 44 5, 11, 20, 43 69 1216 17 18, 19, 22 23, 28, 31 24 25 26 27
Pin Name TxENABLE D11 D10 DVDD DGND D9D6 D5D1 D0
Pin Function Input Pulse that Synchronizes the Data Stream Input Data (Most Significant Bit) Input Data Digital Supply Voltage Digital Ground Input Data Input Data Input Data (Least Significant Bit) No Internal Connection Analog Ground No External Connection* RSET Resistor Connection No External Connection* Analog Supply Voltage
Pin # 29 30 32 33 34 35 36 37 38 39 40 41 42 45 46 47 48
Pin Name I OUTB I OUT PLL GND PLL FILTER PLL SUPPLY CA ENABLE CA DATA CA CLK CS SDO SDIO SCLK SYNC I/O PS0 PS1 REFCLK RESET
Pin Function Complementary Analog Current Output of the DAC True Analog Current Output of DAC PLL Ground PLL Loop Filter Connection PLL Voltage Supply Cable Driver Amp Enable Cable Driver Amp Data Cable Driver Amp Clock Chip Select Serial Data Output Serial Port I/O Serial Port Clock Performs I/O Synchronization Profile Select 0 Profile Select 1 Reference Clock Input Master Reset
NC AGND BG REF BYPASS D A C R SET DAC REF BYPASS AVDD
*In most cases optimal performance is achieved with no external connection. For extremely noisy environments BG REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AVDD (Pin 27).
PIN CONFIGURATION
REFCLK PS1 SYNC I/O CS CA CLK
36 CA DATA 35 CA ENABLE 34 PLL SUPPLY 33 PLL FILTER 32 PLL GND 31 AGND 30 IOUT 29 IOUTB 28 AGND 27 AVDD 26 DAC REF BYPASS 25 DAC RSET 13 14 15 16 17 18 19 20 21 22 23 24
RESET
DVDD DGND
SCLK SDIO
48 47 46 45 44 43 42 41 40 39 38 37
TxENABLE 1 D11 2 D10 3 DVDD 4 DGND 5 D9 6 D8 7 D7 8 D6 9 DVDD 10 DGND 11 D5 12 NC = NO CONNECT
PIN 1 IDENTIFIER
AD9856
TOP VIEW (Not to Scale)
SDO
PS0
4
BG REF BYPASS
D4 D3 D2
NC NC
DGND DVDD NC
AGND
D1 D0
REV. B
AD9856
FUNCTIONAL BLOCK AND MODE DESCRIPTION
Operating Modes Input Data Format
1. Complex quadrature modulator mode. 2. Single tone output mode. Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is 12-bit, twos complement. Complex I/Q symbol component data is required to be at least 2× oversampled, depending upon configuration. Up to 50 Msamples/s @ 200 MHz SYSCLK rate. For DC-80 MHz AOUT operation (200 MHz SYSCLK rate): w/REFCLK Multiplier enabled: 10 MHz50 MHz, programmable via control bus w/REFCLK Multiplier disabled: 200 MHz. Note: For optimum data synchronization, the AD9856 Reference Clock, and the input data clock, should be derived from the same clock source. Programmable in integer steps over the range of 4×20×. Can be disabled (effective REFCLK Multiplier = 1) via control bus. Output of REFCLK Multiplier = SYSCLK rate, which is the internal clock rate applied to the DDS and DAC function. Four pin-selectable, preprogrammed formats. Available for modulation and single tone operating modes. Fixed 4×, selectable 2× and selectable 2×63× range. Interpolating filters that provide upsampling and reduce the effects of the CIC passband roll-off characteristics. When Burst Mode is enabled via the control bus, the rising edge of the applied TxENABLE pulse should be coincident with, and frame, the input data packet. This establishes data sampling synchronization. When continuous mode is enabled via the control bus, the TxENABLE pin becomes an I/Q control line. A Logic "1" on TxENABLE indicates I data is being presented to the AD9856. A Logic "0" on TxENABLE indicates Q data is being presented to the AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sampling capability. Precompensates for SIN(x)/x roll-off of DAC; user bypassable. [I × Cos(t) + Q × Sin(t)] or [I × Cos(t) Q × Sin(t)] (default), configurable via control bus, per profile. Power dissipation reduced to less than 6 mW when Full Sleep Mode active, programmable via control bus.
Input Sample Rate Input Reference Clock Frequency
Internal Reference Clock Multiplier
Profile Select Interpolating Range Half-Band Filters TxENABLE FunctionBurst Mode
TxENABLE FunctionContinuous Mode
Inverse SINC Filter I/Q Channel Invert Full Sleep Mode
REV. B
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