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Details, datasheet, quote on part number:AD9857/PCB
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Datasheet text preview:
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FEATURES 200 MHz Internal Clock Rate 14-Bit Data Path Excellent Dynamic Performance 80 dB SFDR @ 65 MHz ( 100 kHz) AOUT 4 20 Programmable Reference Clock Multiplier Reference Clock Multiplier PLL Lock Detect Indicator Internal 32-Bit Quadrature DDS FSK Capability 8-Bit Output Amplitude Control Single-Pin Power-Down Function Four Programmable, Pin-Selectable Signal "Profiles" SIN(x)/x Correction (Inverse SINC Function) Simplified Control Interface 10 MHz Serial, 2- or 3-Wire SPI-Compatible 3.3 V Single Supply Single-Ended or Differential Input Reference Clock 80-Lead LQFP Surface-Mount Packaging Three Modes of Operation Quadrature Modulator Mode Single-Tone Mode Interpolating DAC Mode
CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter AD9857
APPLICATIONS HFC Data, Telephony, and Video Modems Wireless Base Station Agile, L.O. Frequency Synthesis Broadband Communications GENERAL DESCRIPTION
The AD9857 integrates a high-speed Direct Digital Synthesizer (DDS), a high-performance, high-speed 14-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions onto a single chip, to form a complete quadrature digital upconverter device. The AD9857 is intended to function as a universal I/Q modulator and agile upconverter, single-tone DDS, or interpolating DAC for communications applications, where cost, size, power dissipation, and dynamic performance are critical attributes. The AD9857 offers enhanced performance over the industrystandard AD9856, as well as providing additional features. The AD9857 is available in a space-saving surface-mount package and is specified to operate over the extended industrial temperature range of 40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
I PARALLEL DATA IN (14-BIT) D 14 E M 14 U X Q
INVERSE CIC FILTER
FIXED INTERPOLATOR M U X
PROGRAMMABLE INTERPOLATOR CIC 63 ) M U X
QUADRATURE MODULATOR
AD9857
DAC_RSET M 14 U X 8 IOUT IOUT
INV CIC
(4 )
(2
M U X
INVERSE SINC FILTER
14-BIT DAC
INVERSE CIC CONTROL
INVERSE CIC CLOCK
HALF-BAND CLOCKS
COS
SIN
INTERP CONTROL
INTERP CLOCK
DATA CLOCK
INVERSE SINC CLOCK
DDS CORE
OUTPUT SCALE VALUE
TUNING WORD
32
CONTROL REGISTERS
TIMING & CONTROL
SYNCH
CLOCK
SYSCLK
POWERDOWN LOGIC
PROFILE SELECT LOGIC
M U X
DAC CLOCK
CLOCK MULTIPLIER (4 20 )
MODE CONTROL
REFCLK REFCLK
CIC PDCLK/ TxENABLE RESET OVERFLOW FUD
SERIAL PORT
DIGITAL POWERDOWN
PS1 PS0
PLL LOCK
CLOCK INPUT MODE
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD9857
TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . 5 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 7 Modulated Output Spectral Plots . . . . . . . . . . . . . . . . . . . . 7 Single-Tone Output Spectral Plots . . . . . . . . . . . . . . . . . . . 8 Narrowband SFDR Spectral Plots . . . . . . . . . . . . . . . . . . . 9 Output Constellations . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 11 Quadrature Modulation Mode . . . . . . . . . . . . . . . . . . . . . 11 Single-Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interpolating DAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 SIGNAL PROCESSING PATH . . . . . . . . . . . . . . . . . . . . . 13 Input Data Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Inverse CIC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Fixed Interpolator (4¥) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Programmable (2¥63¥) CIC Interpolating Filter . . . . . . 16 Quadrature Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DDS Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Inverse SINC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output Scale Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14-Bit D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . 18 INPUT DATA PROGRAMMING . . . . . . . . . . . . . . . . . . . Control Interface--Serial I/O . . . . . . . . . . . . . . . . . . . . . . General Operation of the Serial Interface . . . . . . . . . . . . . Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SERIAL INTERFACE PORT PIN DESCRIPTIONS . . . . SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSB/LSB Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes Serial Port Operation . . . . . . . . . . . . . . . . . . . . . . . CONTROL REGISTER DESCRIPTION . . . . . . . . . . . . . PROFILE #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROFILE #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROFILE #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROFILE #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency for the Single-Tone Mode . . . . . . . . . . . . . . . . . Other Factors Affecting Latency . . . . . . . . . . . . . . . . . . . EASE OF USE FEATURES . . . . . . . . . . . . . . . . . . . . . . . . Profile Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Phase of the DDS . . . . . . . . . . . . . . . . . . . . . . Reference Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . PLL Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single or Differential Clock . . . . . . . . . . . . . . . . . . . . . . . CIC Overflow Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clearing the CIC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware-Controlled Digital Power-Down . . . . . . . . . . . Software-Controlled Digital Power-Down . . . . . . . . . . . . Full Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Considerations . . . . . . . . . . . . . . . . . Equivalent I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 21 21 21 21 21 21 21 21 21 22 22 22 23 23 25 25 25 27 27 27 27 27 27 28 28 28 28 28 28 29 29 32 32
2
REV. B
AD9857
SPECIFICATIONS
Parameter
(VS = 3.3 V 5%, RSET = 1.96 k , External reference clock frequency = 10 MHz with REFCLK Multiplier enabled at 20 ).
Temp Test Level Min Typ Max Unit
REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4× REFCLK Multiplier Enabled at 20× Input Capacitance Input Impedance Duty Cycle Duty Cycle with REFCLK Multiplier Enabled Differential Input (VDD/2) ± 200 mV DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Residual Phase Noise @ 1 kHz Offset, 40 MHz AOUT REFCLK Multiplier Enabled at 20× REFCLK Multiplier at 4× REFCLK Multiplier Disabled Voltage Compliance Range Wideband SFDR 1 MHz20 MHz Analog Out 20 MHz40 MHz Analog Out 40 MHz60 MHz Analog Out 60 MHz80 MHz Analog Out Narrowband SFDR 10 MHz Analog Out (± 1 MHz) 10 MHz Analog Out (± 250 kHz) 10 MHz Analog Out (± 50 kHz) 10 MHz Analog Out (± 10 kHz) 65 MHz Analog Out (± 1 MHz) 65 MHz Analog Out (± 250 kHz) 65 MHz Analog Out (± 50 kHz) 65 MHz Analog Out (± 10 kHz) 80 MHz Analog Out (± 1 MHz) 80 MHz Analog Out (± 250 kHz) 80 MHz Analog Out (± 50 kHz) 80 MHz Analog Out (± 10 kHz) MODULATOR CHARACTERISTICS (65 MHz AOUT) (Input Data: 2.5 MS/s, QPSK, 4× Oversampled, INV SINC ON, INV CIC ON) I/Q Offset Error Vector Magnitude INVERSE SINC FILTER (Variation in Gain from DC to 80 MHz, Inverse SINC Filter ON)
Full Full Full 25 °C 25 °C 25 °C 25 °C 25 °C
VI VI VI V V V V V
1 1 1 3 100 50 35 1.45 14 10
200 50 10
65 1.85
MHz MHz MHz pF M % % V Bits mA % FS µA LSB LSB pF dBc/Hz dBc/Hz dBc/Hz V dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C
I I V V V V V V I V V V V V V V V V V V V V V V V
5 8.5
20 0 2
1.6 2 5 107 123 145 0.5 75 65 62 60 87 88 92 94 86 86 86 88 85 85 85 86 +1.0
25 °C 25 °C 25 °C
IV IV V
55
65 0.4 ± 0.1
1
dB % dB
REV. B
3
AD9857SPECIFICATIONS
Parameter SPURIOUS POWER (Off Channel, Measured in Equivalent Bandwidth), Full-Scale Output 6.4 MHz Bandwidth 3.2 MHz Bandwidth 1.6 MHz Bandwidth 0.8 MHz Bandwidth 0.4 MHz Bandwidth 0.2 MHz Bandwidth SPURIOUS POWER (Off Channel, Measured in Equivalent Bandwidth), Output Attenuated 18 dB Relative to Full Scale 6.4 MHz Bandwidth 3.2 MHz Bandwidth 1.6 MHz Bandwidth 0.8 MHz Bandwidth 0.4 MHz Bandwidth 0.2 MHz Bandwidth TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulsewidth Low (tPWL) Minimum Clock Pulsewidth High (tPWH) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Wake-Up Time1 Minimum RESET Pulsewidth High (tRH) Minimum CS Setup Time CMOS LOGIC INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA LOAD) Logic "1" Voltage Logic "0" Voltage POWER SUPPLY VS CURRENT3 (All Power Specs at VDD = 3.3 V, 25°C, REFCLK = 200 MHz) Full Operating Conditions 160 MHz Clock (×16) 120 MHz Clock (×12) Burst Operation (25%) Single-Tone Mode Power-Down Mode Full-Sleep Mode Temp Test Level Min Typ Max Unit 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C IV IV IV IV IV IV 65 67 69 69 70 72 dBc dBc dBc dBc dBc dBc
25 °C 25 °C 25 °C 25 °C 25 °C 25 °C
IV IV IV IV IV IV
51 54 56 59 62 63
dBc dBc dBc dBc dBc dBc
25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C
I I I I I I I I I I IV IV I I V I I
10 30 30 1 30 0 35 1 5 40 2.0 0.8 5 5 3 2.7 0.4
MHz ns ns ms ns ns ns ms SYSCLK2 Cycles ns V V µA µA pF V V
25 °C 25 °C 25 °C 25 °C 25 °C 25 °C 25 °C
I I I I I I I
540 445 345 395 265 71 8
615 515 400 450 310 80 13.5
mA mA mA mA mA mA mA
NOTES 1 Wake-Up Time refers to recovery from Full-Sleep Mode. The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multiplier lock can be determined by observing the signal on the PLL_LOCK pin. 2 SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the Reference Clock Multiplier is used to multiply the external reference frequency, the SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not used, the SYSCLK frequency is the same as the external REFCLK frequency. 3 CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, Auto Power-Down Between Burst On, TxENABLE Duty Cycle = 25%. Specifications subject to change without notice.
4
REV. B
AD9857
ABSOLUTE MAXIMUM RATINGS*
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.7 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . 40°C to +85°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 °C / W JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 ° C / W
*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level I. 100% production tested. II. 100% production tested at 25°C and sample tested at specific temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial operating temperature range.
ORDERING GUIDE Model AD9857AST AD9857/PCB Temperature Range 40°C to +85°C 2 5 °C Package Description Quad Flatpack Evaluation Board Package Option ST-80
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9857 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION
PDCLK/FUD
WARNING!
ESD SENSITIVE DEVICE
CIC_OVRFL PLL_LOCK
TxENABLE
REFCLK REFCLK
RESET
DGND DGND
DGND
DGND
DGND
DGND
AGND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
D13 1 D12 2 D11 3 D10 4 D9 5 D8 6 D7
7
AGND
DVDD
DVDD DVDD
AVDD
DPD
PIN 1 IDENTIFIER
60 59 58 57 56 55 54 53
DIFFCLKEN AGND AVDD NC AGND PLL_FILTER
DVDD 8 DVDD 9 DVDD 10 DGND 11 DGND 12 DGND 13 D6 14 D5 15 D4 16 D3 D2 18 D1 19
17
AD9857
TOP VIEW (Not to Scale)
AVDD AGND 52 NC 51 NC
50 49 48 47 46 45
DAC_RSET DAC_BP AVDD AGND
IOUT IOUT 44 AGND 43 AVDD
42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AGND NC
D0 20
CS SCLK SDIO PS1 PS0 DGND DGND DGND AGND AGND SYNCIO AGND SDO DVDD NC DVDD DVDD AVDD AVDD AVDD
NC = NO CONNECT
REV. B
5
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