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Details, datasheet, quote on part number:AD9859
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Datasheet text preview:
A
FEATURES
400 MSPS 10-Bit, 1.8V CMOS Direct Digital Synthesizer
Preliminary Technical Data
400 MSPS Internal Clock Speed Integrated 10-bit D/A Converter Programmable phase/amplitude dithering 32-bit Tuning Word Phase Noise 50dB @ 130MHz (+/- 100KHz Offset) Aout Serial I/O Control 1.8V Power Supply Software and Hardware controlled power down 48-lead EPAD-TQFP package Support for 5v input levels on most digital inputs
AD9859
PLL REFCLK multiplier (4X to 20X) Internal oscillator, can be driven by a single crystal Phase modulation capability
Multi-Chip Synchronization APPLICATIONS
Agile L.O. Frequency Synthesis FM Chirp Source for Radar and Scanning Systems Test and Measurement Equipment
Functional Block Diagram
Phase Accumulator z -1
DDS Core
Phase Offset
32 19 10
DA C I-set
COS(x) DAC
Aout Aout
Frequency Tuning Word
14
System Clock
Phase Accumulator RESET
14
DDS Clock
z -1
32
32
OSK PwrDwn
Sync
I/O Update Sync Out
M U X 0
SYNC
Timing & Control Logic
4
Control Registers
Oscillator/Buffer
RefClk RefClk
ENABLE
4x-20x Clock Multipler
M U X
System Clock
Crystal Out
IO Port
Reset
REV. PrB 3/4/2003 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
PRELIMINARY TECHNICAL DATA
GENERAL DESCRIPTION
The AD9859 is a Direct Digital Synthesizer (DDS) featuring a 10-bit DAC operating up to 400MSPS. The AD9859 uses advanced DDS technology, coupled with an internal high-speed, high performance D/A converter to form a digitallyprogrammable, complete high-frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9859 is designed to provide fast
AD9859
frequency hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into the AD9859 via a serial I/O port. The AD9859 is specified to operate over the extended industrial temperature range of -40° to +85°C.
ABSOLUTE MAXIMUM RATINGS1
Maximum Junction Temp. ..... +150 °C Vs .......... +4 V Digital Input Voltage....... -0.7 V to +Vs Digital Output Current ...... 5 mA Storage Temperature .. -65 °C to +150 °C Operating Temp. ........... -40 °C to +85 °C Lead Temp. (10 sec. soldering) .. +300 °C JA .......... 38°C/W 15 °C/W JC
* Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
CONTENTS Functional Block Diagram GENERAL DESCRIPTION AD9859 PRELIMINARY ELECTRICAL SPECIFICATIONS AD9859 Pinmap Pin Name I/O Theory of Operation Component Blocks DDS Core Phase Truncation Clock Input Phase Locked Loop (PLL) DAC Output Serial IO Port Register Maps and Descriptions AD9859 Register Map
Default
Control Register Bit Descriptions Control Function Register #1 (CFR1) Control Function Register #1 (CFR2) Other Register Descriptions Amplitude Scale Factor (ASF) Amplitude Ramp Rate (ARR) Frequency Tuning Word 0 (FTW0) Phase Offset Word (POW)
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1 2 4 7 8 8 10 10 10 11 11 12 12 13 13 14 14 15 15 18 20 20 20 20 20
Analog Devices, Inc.
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PRELIMINARY TECHNICAL DATA
AD9859 Frequency Tuning Word 1 (FTW1) Error! Bookmark not defined. Mode of Operation 20 Single Tone Mode 20 Continuous Clear and "Clear and Release" Phase Accumulator Clear Functions 21 Continuous Clear bits 21 Clear and Release function 21 Programming AD9859 Features 21 Phase Offset Control 21 Phase/Amplitude Dithering 21 Shaped On-Off Keying 22 AUTO Shaped On-Off Keying mode operation: 23 OSK Ramp Rate Timer 24 External Shaped On-Off Keying mode operation: 25 Synchronization; Register Updates (I/O UPDATE) 25 Functionality of the SyncClk and I/O UPDATE 25 Figure D- I/O Synchronization Block Diagram 26 Figure E - I/O Synchronization Timing Diagram 26 Synchronizing Multiple AD9859s 26 Using a Single Crystal To Drive Multiple AD9859 Clock InputsError! Bookmark not defined. Serial Port Operation 28 Instruction Byte 29 Serial Interface Port Pin Description 30 MSB/LSB Transfers 30 Example Operation 30 Notes on Serial Port Operation 31 Power Down Functions of the AD9859 31 Digital and Input Clock Power Down 32 AD9859 Application Suggestions 32
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Analog Devices, Inc.
PRELIMINARY TECHNICAL DATA
AD9859 PRELIMINARY ELECTRICAL SPECIFICATIONS
Parameter
REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4X REFCLK Multiplier Enabled at 20X Input Capacitance Input Impedance Duty Cycle Duty Cycle with REFCLK Multiplier Enabled DAC OUTPUT CHARACTERISTICS Resolution Full Scale Output Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Residual Phase Noise @ 1 kHz Offset, 40 MHz Aout REFCLK Multiplier Enabled @ 20× REFCLK Multiplier Enabled @ 4× REFCLK Multiplier Disabled Voltage Compliance Range Wideband SFDR: 1 20 MHz Analog Out 20 40 MHz Analog Out 40 60 MHz Analog Out 60 80 MHz Analog Out 80 100 MHz Analog Out 100 120 MHz Analog Out 120 140 MHz Analog Out 140 160 MHz Analog Out Narrow Band SFDR 10 MHz Analog Out (±1 MHz) 10 MHz Analog Out (±250 kHz) 10 MHz Analog Out (± 50 kHz) 10 MHz Analog Out (± 10 kHz) 65 MHz Analog Out (± 1 MHz) 65 MHz Analog Out (± 250 kHz) 65 MHz Analog Out (± 50 kHz) 65 MHz Analog Out (± 10 kHz) 80 MHz Analog Out (± 1 MHz) 80 MHz Analog Out (± 250 kHz) 80 MHz Analog Out (± 50 kHz) 80 MHz Analog Out (± 10 kHz) 100 MHz Analog Out (± 1 MHz) 100 MHz Analog Out (± 250 kHz) 100 MHz Analog Out (± 50 kHz) 100 MHz Analog Out (± 10 kHz) 120 MHz Analog Out (± 1 MHz) 120 MHz Analog Out (± 250 kHz) 120 MHz Analog Out (± 50 kHz) 120 MHz Analog Out (± 10 kHz) 140 MHz Analog Out (± 1 MHz) 140 MHz Analog Out (± 250 kHz) 140 MHz Analog Out (± 50 kHz) 140 MHz Analog Out (± 10 kHz) 160 MHz Analog Out (± 1 MHz) 160 MHz Analog Out (± 250 kHz) REV. PrB 3/4/03
AD9859
(Unless otherwise noted: (VDD=+1.8 V ±5%, RSET=1.96 k, External reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 20×)
Temp Test Level Min
FULL FULL FULL +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C VI VI VI V V V V 1 20 4 3 100 50 35 10 10 I I V V V V V V I V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Analog Devices, Inc. -10 1 2 5 -89 -105 -116 AVDD0.375 AVDD + 0.25V 65 15 +10 0.6
AD9859 Typ Max
400 100 20
Units
MHz MHz MHz pF M % % Bits mA %FS µA LSB LSB pF dBc/Hz dBc/Hz dBc/Hz V dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
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PRELIMINARY TECHNICAL DATA
Parameter 160 MHz Analog Out (± 50 kHz) 160MHz Analog Out (± 10 kHz)
TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low (tPWL) Minimum Clock Pulse Width High (tPWH) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Wake-Up Time2 Minimum Reset Pulsewidth High (tRH) CMOS LOGIC INPUTS Logic "1" Voltage @ DVDD = 1.8V Logic "0" Voltage @ DVDD = 1.8V Logic "1" Voltage @ DVDD = 3.3V Logic "0" Voltage @ DVDD = 3.3V Logic "1" Current Logic "0" Current Input Capacitance CMOS LOGIC OUTPUTS (1mA load) Logic "1" Voltage (include for both DVDD) Logic "0" Voltage POWER SUPPLY +VS Current Full Operating Conditions 400 MHz Clock 120 MHz Clock Power-Down Mode Full-Sleep Mode
AD9859
Test Level V V
IV IV IV IV IV IV IV IV IV IV I I I I V
Temp +25°C +25°C
FULL FULL FULL FULL FULL FULL FULL FULL FULL FULL +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C
Min
Typ
Max
Units dBc dBc
25 7 7 5 10 0 25 1 5
MHz ns ns ns ns ns ns ms SYSCLK cycles3 V V µA µA pF V V mA mA mA mA mA mA
TBD % % 3 12 12
I I I I I I I I
TBD 0.4 30 TBD TBD TBD TBD TBD
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time affect device reliability. 2 Wake-Up Time refers to recovery from analog power down modes (see Power Down Modes of Operation). The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. 3 SYSCLK refers to the actual clock frequency used on-chip by the AD9859. If the Reference Clock Multiplier is used to multiply the external reference frequency, then the SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not used, then the SYSCLK frequency is the same as the external REFCLK frequency. Specifications are subject to change without notice. EXPLANATION OF TEST LEVELS I II III IV V VI 100% Production Tested. 100% Production Tested at +25°C and sample tested at specified temperatures. Sample Tested Only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. Devices are 100% production tested at +25°C and guaranteed by design and characterization testing for industrial operating temperature range.
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Analog Devices, Inc.
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