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Details, datasheet, quote on part number:AD9860BST
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a
Mixed Signal Front-End (MxFETM) Processor for Broadband Communications AD9860/AD9862
FUNCTIONAL BLOCK DIAGRAM
LO W PAS S DE C IM ATI O N F ILT E R
VIN+ A VIN- A 1x
P GA
Preliminary Technical Data
FEATURES Mixed Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path includes: Two 10/12-Bit, 64 MSPS Sampling A/D Converter with Internal or External Independent References, Input Buffers, Programmable Gain Amplifiers, Low-Pass Decimation Filters and a Digital Hilbert Block Transmit Signal Path includes: Two 12/14-bit, 128 MSPS D/A Converter with Programmable Full Scale Output Current, Channel Independent fine gain and offset control, Digital Hilbert and Interpolation Filters, Digitally Tunable Real or Complex Up-Converters Delay-Locked Loop clock multiplier and Integrated Timing Generation circuitry allow for single crystal or clock operation Programmable Output Clocks, Serial Programmable Interface, Programmable Sigma Delta, three Auxiliary DAC outputs and two Auxiliary ADCs with dual multiplexed inputs APPLICATIONS Broadband Wireless Systems Fixed Wirekess, WLAN, MMDS, LMDS Broadband Wireline Systems Cable Modems, VDSL, PowerPlug Digital Communications Set-Top Boxes, Data Modems GENERAL DESCRIPTION
AD C AD C
H IL B E RT F ILT E R
R x A D a ta [0:11 ]
VIN+ B VIN- B
1x
P GA
LOGIC LOW
SigDe lt
AUX_ D AC _A AUX_ D AC _B AUX_ D AC _C AU X D AC AU X D AC AU X D AC R x Pat h Timing AU X AD C AU X_ AD C_ B AU X_ ADC _ C AU X AD C AU X_ AD C_ D Tx Path Tim in g
R x B D a ta [0:11 ]
SPI REG ISTERS
SPI Inter fa c e
AU X_ ADC _ A
C LOC K D I STR I BU T IO N BL OC K
DLL
1 x , 2 x, 4 x
O SC 1 O SC 2
C LK OU T1 CL KO UT2
I OU T+ A IO UT- A I O UT+ B IO UT- B
PGA PGA
D ig ita l Q u a dra tu re M ix e r
DAC
D i gita l Q u a d ra tu re M ixe r I HIL B E RT F ILTE R
Tx D ata [0 :1 3]
DAC
Q LO W PA S S IN T E R P O L ATI O N FI LT E R F s /4 , N CO F s /8
The output data bus can be multiplexed to accommodate a variety of interface types. The AD9860/2 transmit path (Tx) consits of two channels that contain high performance, 12/14-bit, 128 MSPS Digital to Analog converters (DAC), programmable gain amplifiers (TxPGA), interpolation filters, a Hilbert filter and digital mixers for complex or real signal frequency modulation. The Tx latch and demultiplexer circuitry can process real or I&Q data. Interpolation rates of 2x and 4x are available to ease requirements on an external reconstruction filter. For single channel systems, the digital Hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. The two 12/14-bit, high performance DACs produce an output signal which can be scaled over a 20 dB range by the TxPGA. A programmable delay-locked loop (DLL) clock multiplier and integrated timing circuits enable the use of a single external reference clock or an external crystal to generate clocking for all internal blocks and also provides two external clock outputs. Additional features include a programmable sigma-delta output, four auxiliary ADC inputs and three auxiliary DAC outputs. Device programmability is facilitated by a serial port interface (SPI) combined with a register bank. The AD9860/2 is available in a space saving 128 pin LQFP.
The AD9860 and AD9862 (AD9860/2) are versatile integrated mixed signal front-ends (MxFETM) that are optimized for broadband communication markets. The AD9860/2 are cost effective mixed signal solutiona for wireless or wireline, standards based or proprietary broadband modem systems where dynamic performance, power dissipation, cost and size are all critical attributes. The AD9860 has 10 bit ADCs and 12 bit DACs, the AD9862 has 12 bit ADCs and 14 bit DACs. The AD9860/2 receive path (Rx) consists of two channels that each include a high performance, 10/12-bit, 64 MSPS Analog to Digital converter (ADC), input buffer, Programmable Gain Amplifier (RxPGA), digital Hilbert Filter and a decimation filter. The Rx can be used to receive real, diversity or I&Q data at baseband or low IF. The input buffers provide a constant input impedance for both channels to ease impedance matching with external components (e.g. SAW filter). The RxPGA provides a 20 dB gain range for both channels.
0 4 / 15 / 2 0 0 2
REV PrB
One Technology Way, P O. Box 9106, Norwood, MA 02062-9106, U.S.A. . Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PRELIMINARY TECHNICAL DATA AD9860/AD9862
Tx PARAMETERS 12-BIT / 14-BIT DAC CHARACTERISTICS Resolution Maximum Update Rate Full-Scale Output Current Gain Error (using internal reference) Offset Error Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1kHz Offset, 6MHz Tone Crystal & OSC IN Multiplier Enabled at 4× Output Voltage Compliance Range Transmit TxPGA CHARACTERISTICS Gain Error Gain Range Step Size Accuracy Step Size Tx DIGITAL FILTER CHARACTERISTICS Hilbert Filter Pass Band (< 0.1 dB ripple) 2x/4x Interpolator Stop Band1 Dynamic Performance (Aout=0dB FS, f= 6 MHz Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Signal-to-Noise and Distortion Ratio (SINAD) 12 MHz Analog Out, Iout = 20 ma Differential Phase Differential Gain Wideband SFDR (to Nyquist, 64 MHz Max) 6 MHz Analog Out, Iout=2mA 6 MHz Analog Out, Iout=20mA 12 MHz Analog Out, Iout=20mA Narrowband SFDR (3 MHz Window): 12 MHz Analog Out, Iout=2mA 12 MHz Analog Out, Iout=20mA Temp n.a. FULL 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC FULL 25ºC 25ºC 2 5 ºC 25ºC FULL FULL FULL FULL FULL 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC
(VA = +3.3V ± 5%, VD = +3.3V ± 10%, fDAC = 128 MHz, fADC = 64 MHz Normal Timing Mode, 2x DLL setting, RSET = 4 k, 50 DAC Load)
Test Level n.a. I I I I III III III III II I I I I II II I I I III III III III III III III 12.5 128 2 -3 -1 Min AD9860/2 Typ Max 12/14 20 3 1 Units Bits MSPS mA %FS %FS V LSB LSB pF dBc/Hz V dB dB dB dB 38 ±38 TBD/71 TBD/-77.6 TBD/65 <0.1 <1 TBD TBD/80 TBD/80 TBD 88 % fDATA2 % fDATA dB dB dB Degree LSB dBc dBc dBc dBc dBc
0.14 1.23 ±1 ±1/±2 5 -115
-0.5 ±TBD 20 ±TBD 0.08
1.5
TBD
TBD
TBD
NOTES: 1. Interpolation Filter Stopband is defined by image suppression of 50 dB or greater. 2. % fDATA refers to the input data rate of the digital block Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
(VA = +3.3V ± 5%, VD = +3.3V ± 10%, fDAC = 128 MHz, fADC = 64 MHz Normal Timing Mode, 2x DLL setting, RSET = 4 k, 50 DAC Load)
Rx PARAMETERS RECEIVE BUFFER Input Resistance (differential) Input Capacitance (each input) Maximum Input Bandwidth (-3dB) Analog Input Range (Best noise performance) Analog Input Range (Best THD performance) RECEIVE PGA CHARACTERISTICS Gain Error Gain Range Step Size Accuracy Step Size Input Bandwidth (-3dB, Rx buffer bypassed) 10-BIT / 12-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Aperture Delay Aperture Uncertainty (Jitter) Input Referred Noise Reference Voltage Error REFT-REFB Error (1V) Dynamic Performance (Ain=-0.5dBFS, f= 6 MHz) Signal-to-Noise Ratio Signal-to-Noise and Distortion Ratio Total Harmonic Distortion Worst Harmonic (2nd through 5th) Spurious Free Dynamic Range Channel-To-Channel Isolation Tx-to-Rx (Aout=0dBFS, fout = 7 MHz) Rx channel crosstalk (f1=6MHz, f2=9MHz) Temp FULL FULL FULL FULL FULL 25ºC 25ºC 25ºC 25ºC 25ºC n.a. FULL 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25°C 25°C 25°C Full 25°C 25ºC 25ºC Test Level III III III II II I I I I III n.a. I II II I I III III III I III III III III III II II Min
AD9860/AD9862
AD9860/2 Typ Max 200 5 140 2 1 ±1 20 ±0.2 1 250 10/12 64 ±0.75 ±0.75/±1.5 ±0.1 ±0.2 2.0 1.2 TBD ±6 TBD/66.5 TBD/65.5 -75 -75.5 TBD/75.5 >90 >80 TBD Units Ohm pF MHz Vpp Diff Vpp Diff dB dB dB dB MHz Bits MHz LSB LSB % FSR % FSR ns ps RMS µV mV dBc dBc dBc dBc dBc dB dB
NOTES Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD9860/AD9862
PARAMETER CMOS LOGIC INPUTS Logic "1" Voltage, Vih Logic "0" Voltage, Vil Logic "1" Current Logic "0" Current Input Capacitance CMOS LOGIC OUTPUTS (1mA Load) Logic "1" Voltage, Voh Logic "0" Voltage, Vol POWER SUPPLY Analog Supply Currents Tx Path (both channels) Tx Path Sleep Mode Rx Path (both channels, input buffer enabled) Rx Path (both channels, input buffer disabled) Rx Path Powered Down DLL Digital Supply Current Tx Path (all processing blocks bypassed) Tx Coarse Modulation Tx 2x Interpolation Tx 4x Interpolation Tx Fine Modulation Tx Quiet (Tx_Blank_In asserted) Rx Path (all processing blocks bypassed) Rx Decimation Filter1 Rx Hilbert Filter Temp 25 º C 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC
(VA = +3.3V ± 5%, VD = +3.3V ± 10%, fDAC = 128 MHz, fADC = 64 MHz Normal Timing Mode, 2x DLL setting, RSET = 4 k, 50 DAC Load)
Test Level III III II II III II II Min
DRVDD -0.7
AD9860/2 Typ Max
Units V V µA µA pF V V
0.4 12 12 3
DRVDD -0.6
0.4
25ºC 25ºC 25 º C 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC 25ºC
II II II II II II II II II II II II II II II
55 0 275 250 10 12 30 25 20 25 20 33 30 10 10
TBD TBD
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
TIMING CHARACTERISTICS (20pF Load) Wake-Up Time Minimum RESET Pulsewidth Low (tRL) Digital Output Rise-/Fall Time DLL Output Clock DLL Output Duty Cycle TX- /RX- Interface (see Figures 11 and 12) TXSYNC/TXIQ set up time (tTx1 , tTx3) TXSYNC/TXIQ hold time (tTx2 , tTx4) RXSYNC/RXIQ/IF to valid time(tRx1 , tRx3) RXSYNC/RXIQ/IF hold time (tRx2 , tRx4) Serial Control Bus (see Figures 1 and 2) Maximum SCLK Frequency (fSCLK) Minimum Clock Pulsewidth High (tHI) Minimum Clock Pulsewidth Low (tLOW) Maximum Clock Rise/Fall Time Minimum Data/SEN Setup Time (tS) Minimum SEN/Data Hold Time (tH) Minimum Data/SCLK Setup Time (tDS) Minimum Data Hold Time (tDH) Output Data Valid/SCLK Time(tDV) n.a. n.a. 25ºC 25ºC 25ºC 25 º C 25 º C 25 º C 25 º C Full Full Full Full Full Full Full Full Full n.a. n.a. III III III III III III III III III III III III III III III III 5 2.8 32 50 3 3 5.2 0.2 16 30 30 1 25 TBD TBD TBD TBD 4 128 TBD Clock Cycles Clock Cycles ns MHz % ns ns ns ns MHz ns ns ms ns ns ns ns ns
NOTES: 1. Enabling the decimation filter reduces Rx Path Digital current Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
(VA = +3.3V ± 5%, VD = +3.3V ± 10%, fDAC = 128 MHz, fADC = 64 MHz Normal Timing Mode, 2x DLL setting, RSET = 4 k, 50 DAC Load)
Test Level III
AD9860/AD9862
Min AD9860/2 Typ Max 7 Units cycles
PARAMETER ADC Timing Latency (all digital processing blocks disabled) DAC Timing Output Propagation Delay (TPD) Output Settling Time (TST) (to 0.1%)
Temp +25ºC
+25ºC +25ºC
III III
TBD 35
ns ns
AUX_ADC_A2 AUX_ADC_REF AUX_ADC_B1 AUX_ADC_B2 AVDD (Rx) AVDD (Rx) AGND (Rx) REFT_A
REFB_A AGND (Rx) AVDD (Rx) AVDD (Rx) AGND (Rx) VIN+A VIN-A AGND (Rx)
AGND (Rx) VREF AGND (Rx) AGND (Rx) VIN-B VIN+B AGND (Rx) AVDD (Rx)
AUX_ADC_A1 AGND (Aux) AVDD (Aux) AVDD (SD) SigDelt AUX_DAC_A AUX_DAC_B AUX_DAC_C AGND (SD) DLL_Lock AGND (DLL) NC AVDD (DLL) OSC1 OSC2 AGND (DLL) CLKSEL AVDD (Tx) AGND (Tx) AVDD (Tx) REFIO FSADJ AVDD (Tx) AGND (Tx) IOUT-A IOUT+A AGND (Tx) AGND (Tx) IOUT+B IOUT-B AGND (Tx) AVDD (Tx) DVDD DGND DGND DVDD Tx11/13 (MSB) Tx10/12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AVDD (Rx) AGND (Rx)
AD9860/AD9862 Pinout Configuration 128 LQFP T o p V ie w
REFB_B REFT_B AGND (Rx) AVDD (Rx) AVDD (Rx) AUX_SPI_csb AUX_SPI_clk AUX_SPI_do DGND DVDD RxSYNC D9/D11B (MSB) D8/D10B D7/D9B D6/D8B D5/D7B D4/D6B D3/D5B D2/D4B D1/D3B D0/D2B NC/D1B NC/D0B D9/D11A (MSB) D8/D10A D7/D9A D6/D8A D5/D7A D4/D6A D3/D5A D2/D4A D1/D3A D0/D2A NC/D1A NC/D0A DGND DVDD CLKOUT1
NC = No Connect pins
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39 40 41 42 43 44 45 46 47 Tx1/3 48 Tx0/2 49 NC/Tx1 NC/Tx0 50 51 TxSYNC DGND 52 DVDD 53 SCLK 54 55 SDO 56 SDIO 57 SEN 58 DGND 59 DVDD 60 DGND 61 DVDD M D /TxBLAN K 62 OE 63 RESET CLKOUT2 64 Tx9/11 Tx8/10 Tx7/9 Tx6/8 Tx5/7 Tx4/6 Tx3/5 Tx2/4
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