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Details, datasheet, quote on part number:AD9861
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Datasheet text preview:
Mixed-Signal Front-End (MxFETM) Baseband Transceiver for Broadband Applications AD9861
FEATURES
Receive path includes dual 10-bit analog-to-digital converters with internal or external reference, 50 MSPS and 80 MSPS versions Transmit path includes dual 10-bit, 200 MSPS digital-toanalog converters with 1×, 2×, or 4× interpolation and programmable gain control Internal clock distribution block includes a programmable phase-locked loop and timing generation circuitry, allowing single-reference clock operation 20-pin flexible I/O data interface allows various interleaved or noninterleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode Configurable through register programmability or optionally limited programmability through mode pins Independent Rx and Tx power-down control pins 64-lead LFCSP package (9 mm × 9 mm footprint) 3 configurable auxiliary converter pins
VIN+A VINA VIN+B VINB ADC ADC DATA MUX AND LATCH Rx DATA
FUNCTIONAL BLOCK DIAGRAM
LOW-PASS INTERPOLATION FILTER IOUT+A IOUTA IOUT+B IOUTB DAC DAC DATA LATCH AND DEMUX
I/O INTERFACE CONFIGURATION BLOCK
I/O INTERFACE CONTROL FLEXIBLE I/O BUS [0:19]
Tx DATA
AUX ADC AUX DAC ADC CLOCK AUX DAC CLKIN
DAC CLOCK
PLL
APPLICATIONS
Broadband access Broadband LAN Communications (modems)
AUX ADC
AD9861
AUX DAC
03606-0-001
Figure 1.
GENERAL DESCRIPTION The AD9861 is a member of the MxFE family--a group of integrated converters for the communications market. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC®). Two speed grades are available, -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market. The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches. A flexible, bidirectional 20-bit I/O bus accommodates a variety
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
of custom digital back ends or open market DSPs. In half-duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin count and, therefore, reduces the required package size on the AD9861 and the device to which it connects. The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer, and twos complement data format). The AD9861 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into tightly spaced applications such as PCMCIA cards
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9861 TABLE OF CONTENTS
Tx Path Specifications.... 3 Rx Path Specifications.... 4 Power Specifications....... 5 Digital Specifications...... 5 Timing Specifications..... 6 Absolute Maximum Ratings... 7 ESD Caution.......... 7 Pin Configuration and Pin Function Descriptions.... 8 Typical Performance Characteristics .......... 10 Terminology ... 21 Theory of Operation .... 22 System Block ....... 22 Rx Path Block...... 22 Tx Path Block...... 24 Auxiliary Converters......... 27 Digital Block........ 30 Programmable Registers... 42 Clock Distribution Block .......... 45 Outline Dimensions ..... 49 Ordering Guide ........ 50
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 52
AD9861 Tx PATH SPECIFICATIONS
Table 1. AD9861-50 and AD9861-80 FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 k; differential load resistance of 100 1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V, unless otherwise noted
Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain Mismatch Error Offset Mismatch Error Reference Voltage Output Capacitance Phase Noise (1 kHz Offset, 6 MHz Tone) Output Voltage Compliance Range TxPGA Gain Range TxPGA Step Size Tx PATH DYNAMIC PERFORMANCE (IOUTFS = 20 mA; FOUT = 1 MHz) SNR SINAD THD SFDR, Wideband (DC to Nyquist) SFDR, Narrowband (1 MHz Window)
1
Temp Full Full Full Full 25°C Full Full Full 25°C Full Full Full
Test Level IV IV IV V IV IV V V V IV V V
Min
Typ 10
Max
Unit Bits MHz mA
200 20 1% 3.5 0.1 1.23 5 115 1.0 20 0.10 +1.0 +3.5 +0.1
% FS % FS V pF dBc/Hz V dB dB
Full Full Full Full Full
IV IV IV IV IV
60.2 59.7 64.6 72.5
60.8 60.7 -77.5 76.0 81.0
-65.8
dB dB dBc dBc dBc
See Figure 2 for description of the TxDAC termination scheme.
TxDAC 50 50
03606-0-030
Figure 2. Diagram Showing Termination of 100 Differential Load for Some TxDAC Measurements
Rev. 0 | Page 3 of 52
AD9861 Rx PATH SPECIFICATIONS
Table 2. AD9861-50 and AD9861-80 FADC = 50 MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3V, unless otherwise noted
Parameter Rx PATH GENERAL Resolution Maximum ADC Sample Rate Gain Mismatch Error Offset Mismatch Error Reference Voltage Reference Voltage (REFTREFB) Error Input Resistance (Differential) Input Capacitance Input Bandwidth Differential Analog Input Voltage Range Rx PATH DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Aperature Delay Aperature Uncertainty (Jitter) Input Referred Noise AD9861-50 Rx PATH DYNAMIC PERFORMANCE (VIN = 0.5 dBFS; FIN = 10 MHz) SNR SINAD SINAD THD (Second to Ninth Harmonics) SFDR, Wideband (DC to Nyquist) Crosstalk between ADC Inputs AD9861-80 Rx PATH DYNAMIC PERFORMANCE (VIN = 0.5 dBFS; FIN = 10 MHz) SNR SINAD THD (Second to Ninth Harmonics) SFDR, Wideband (DC to Nyquist) Crosstalk between ADC Inputs Temp Full Full Full Full Full Full Full Full Full Full 25°C 25°C 25°C 25°C 25°C Test Level V IV V V V IV V V V V V V V V V Min Typ 10 50/80 ±0.2 ±0.1 1.0 ±6 2 5 30 2 ±0.75 ±0.75 2.0 1.2 450 Max Unit Bits MSPS % FS % FS V mV k pF MHz V p-p differential LSB LSB ns ps rms uV
30
+30
Full Full 25°C Full Full Full
IV IV IV IV IV V
55.5 55.6 58.5 65.7
60 60 60 -71.5 73.5 80
-64.6
dBc dBc dBc dBc dBc dB
Full Full Full Full Full
IV IV IV IV V
55.4 52.7
59.5 59.0 -67 67 80
dBc dBc dBc dBc dB
Rev. 0 | Page 4 of 52
AD9861 POWER SPECIFICATIONS
Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3.3 V; FCLKIN = 50 MHz; PLL 4× setting; normal timing mode
Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS TxPath (20 mA Full-Scale Outputs) TxPath (2 mA Full-Scale Outputs) Rx Path (-80, at 80 MSPS) RxPath (-80, at 40 MSPS, Low Power Mode) RxPath (-80, at 20 MSPS, Ultralow Power Mode) Rx Path (-50, at 50 MSPS) RxPath (-50, at 50 MSPS, Low Power Mode) RxPath (-50, at 16 MSPS, Ultralow Power Mode) TxPath, Power-Down Mode RxPath, Power-Down Mode PLL DIGITAL SUPPLY CURRENTS TxPath, 1× Interpolation, 50 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 2× Interpolation, 100 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 4× Interpolation, 200 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode RxPath Digital, Half-Duplex 24 Mode Temp Full Full
Full
Test Level IV IV
IV
Min 2.7 2.7
2.7
Typ
Max 3.6 3.6
3.6
Unit V V
V
Full Full Full Full Full Full Full Full Full Full Full Full
V V V V V V V V V V V V
70 20 165 82 35 103 69 28 2 5 12 20
mA mA mA mA mA mA mA mA mA mA mA mA
Full
V
50
mA
Full
V
80
mA
Full
V
15
mA
DIGITAL SPECIFICATIONS
Table 4. AD9861-50 and AD9861-80
Parameter LOGIC LEVELS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Output Logic High Voltage, VOH (1 mA Load) Output Logic Low Voltage, VOL (1 mA Load) DIGITAL PIN Input Leakage Current Input Capacitance Minimum RESET Low Pulse Width Digital Output Rise/Fall Time Temp Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV IV Min DRVDD 0.7 0.4 DRVDD 0.6 0.4 12 3 5 2.8 4 Typ Max Unit V V V V µA pF Input Clock Cycles ns
Rev. 0 | Page 5 of 52
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