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Details, datasheet, quote on part number:AD9865
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Datasheet text preview:
Broadband Modem Mixed Signal Front End AD9865
FEATURES
Low cost 3.3 V CMOS MxFETM for broadband modems 10-bit D/A converter 2×/4× interpolation filter 200 MSPS DAC update rate Integrated 23 dBm line driver with 19.5 dB gain control 10-bit, 80 MSPS A/D converter -12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz) Third order programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Backward compatible with AD9975 and AD9875 Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in 64-lead chip scale package or bare die
FUNCTIONAL BLOCK DIAGRAM
IOUT_P+ IOUT_P
AD9865
PWR DWN MODE TXEN/SYNC TXCLK ADIO[9:4]/ Tx[5:0] 10
2-4X
TxDAC
IAMP 0 TO 12dB
IOUT_G+ IOUT_N+ IOUT_N IOUT_G
0 TO 7.5dB CLK SYN.
CLKOUT_1 CLKOUT_2 2M CLK MULTIPLIER OSCIN XTA L
ADIO[3:0]/ Rx[5:0] RXE/SYNC RXCLK AGC[5:0] SPI 6 4 REGISTER CONTROL 0 TO 6dB = 1dB 6 TO 18dB 6 TO 24dB = 6dB = 6dB
04493-0-001
10
ADC 80MSPS
2-POLE LPF
RX+
1-POLE LPF
RX
APPLICATIONS
Powerline networking VDSL and HPNA
Figure 1.
GENERAL DESCRIPTION
The AD9865 is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make it well suited for half- and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus often allowing the AD9865 to replace discrete ADC and DAC solutions. Power saving modes include the ability to reduce power consumption of individual functional blocks or to power down unused blocks in half-duplex applications. A serial port interface (SPI®) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source. The Tx signal path consists of a bypassable 2×/4× low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier. The current amplifier (IAMP) can be configured as a current or voltage mode line driver (with two external npn transistors) capable of delivering in excess of 23 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps. The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of -12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/ rtHz for gain settings beyond 36 dB. The receive path LPF cut-off frequency can either be set over a 15 MHz to 35 MHz range or simply bypassed. The 10-bit ADC achieves excellent dynamic performance over a 5 MSPS to 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization. The AD9865 provides a highly integrated solution for many broadband modems. It is available in a space-saving 64-pin chip scale package and is specified over the commercial (-40°C to +85°C) temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9865 TABLE OF CONTENTS
Specifications.... 3 Tx Path Specifications......... 3 Rx Path Specifications......... 4 Power Supply Specifications ....... 5 Digital Specifications .......... 6 Serial Port Timing Specifications..... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ........ 7 Full-Duplex Data Interface (Tx and Rx Port) Timing Specifications ........ 8 Absolute Maximum Ratings... 9 Thermal Characteristics ..... 9 ESD Caution.......... 9 Pin Configuration and Function Descriptions... 10 Typical Performance Characteristics .......... 12 Rx Path Typical Performance Characteristics ...... 12 TxDAC Path Typical Performance Characteristics ...... 16 IAMP Path Typical Performance Characteristics ......... 18 Serial Port ....... 19 Register Map Description ......... 21 Serial Port Interface (SPI) ......... 21 Digital Interface ...... 23 Half-Duplex Mode ............ 23 Full-Duplex Mode .... 24 RxPGA Control ........ 25 TxPGA Control ........ 27 Transmit Path .......... 28 Digital Interpolation Filters ...... 28 TxDAC and IAMP Architecture..... 28 Tx Programmable Gain Control .... 30 TxDAC Output Operation........ 30 IAMP Current Mode Operation .... 30 IAMP Voltage Mode Operation ..... 31 IAMP Current Consumption Considerations...... 32 Receive Path ... 33 Rx Programmable Gain Amplifier.......... 33 Low-Pass Filter ......... 34 Analog to Digital Converter (ADC)....... 35 AGC Timing Considerations.... 36 Clock Synthesizer ......... 37 Power Control and Dissipation .... 39 Power-Down ....... 39 Half-Duplex Power Savings ...... 39 Power Reduction Options......... 40 Power Dissipation .... 42 Mode Select upon Power-Up and Reset.......... 42 Analog and Digital Loop-back Test Modes .... 43 PCB Design Considerations.......... 44 Component Placement..... 44 Power Planes and Decoupling ........ 44 Ground Planes .......... 44 Signal Routing .......... 44 Evaluation Board .......... 46 Outline Dimensions ..... 47 Ordering Guide ........ 47
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 48
AD9865 SPECIFICATIONS
Tx PATH SPECIFICATIONS
Table 1. AVDD = 3.3 V ±5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; fOSCIN = 50 MHz, fDAC = 200 MHz, RSET = 2.0 k, unless otherwise noted
Parameter TxDAC DC CHARACTERISTICS Resolution Update Rate Full-Scale Output Current (IOUTP_FS) Gain Error1 Offset Error Voltage Compliance Range TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy Gain Range Error TxDAC AC CHARACTERISTICS2 Fundamental Signal-to-Noise and Distortion Signal-to-Noise Ratio THD SFDR IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN- IOUTG Full-Scale Current = IOUTG+ + IOUTG- AC Voltage Compliance Range IAMPN AC CHARACTERISTICS3 Fundamental IOUTN SFDR (Third Harmonic) IAMP GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy IOUTN Gain Range Error REFERENCE Internal Reference Voltage4 Reference Error Reference Drift Tx DIGITAL FILTER CHARACTERISTICS (2× Interpolation) Latency (Relative to 1/fDAC) -0.2 dB Bandwidth -3 dB Bandwidth Stop-Band Rejection (0.289 fDAC to 0.711 fDAC) Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation) Latency (Relative to 1/ FDAC) -0.2 dB Bandwidth Temp Full Full Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Test Level Min Typ 10 II IV I V 2 ±2 2 -1 V V V IV V -7.5 0 0.5 Monotonic ±2 0.5 63.1 63.2 -77.7 79.3 +1.5 200 25 Max Unit Bits MSPS mA % FS uA V dB dB dB dB dBm dBc dBc dBc dBc mA mA V dBm dBc dB dB dB dB dB V 3.4 % ppm/oC Cycles fOUT/fDAC fOUT /fDAC dB Cycles fOUT/fDAC
Full Full Full Full Full Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full Full Full Full Full Full Full Full
IV IV IV IV IV IV IV
62.0 62.5 67.1 2 2 1
-67.0
105 150 7 13 45.2 -19.5 0 0.5 Monotonic 0.5 1.23 0.7 30 43 0.2187 0.2405 50 96 0.1095
IV V V V IV V I V V V V V V V V
43.3
Rev. 0 | Page 3 of 48
AD9865
Parameter -3 dB Bandwidth Stop Band Rejection (0.289 fOSCIN to 0.711 fOSCIN) PLL CLK MULTIPLIER OSCIN Frequency Range Internal VCO Frequency Range Duty Cycle OSCIN Impedance CLKOUT1 Jitter5 CLKOUT2 Jitter6 CLKOUT1 and CLKOUT2 Duty Cycle7 Temp Full Full Full Full Full 25°C 25°C 25°C Full Test Level V V IV IV II V III III III Min Typ 0.1202 50 Max Unit fOUT /fDAC dB MHz MHz % /pF ps rms ps rms %
5 20 40 100//3 12 6 45
80 200 60
55
1 2 3
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input). TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 , FOUT = 5 MHz, 4x interpolation. IOUN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation. 4 Use external amplifier to drive additional load. 5 Internal VCO operates at 200 MHz , set to divide-by-1. 6 Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN. 7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS
Table 2. AVDD = 3.3 V ±5%, DVDD = CLKVDD = DRVDD = 3.3 V ±10%; half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted
Parameter Rx INPUT CHARACTERISTICS Input Voltage Span (RxPGA Gain = -10 dB) Input Voltage Span (RxPGA Gain = +48 dB) Input Common-Mode Voltage Differential Input Impedance Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB) Input Voltage Noise Density (RxPGA Gain = 36 dB, f-3 dBF = 26 MHz) Input Voltage Noise Density (RxPGA Gain = 48 dB, f-3 dBF = 26 MHz) RxPGA CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy Gain Range Error RxLPF CHARACTERISTICS Cutoff Frequency (f-3 dBF ) Range Attenuation at 55.2 MHz with f-3 dBF = 21 MHz Pass-Band Ripple Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS ADC DC CHARACTERISTICS Resolution Conversion Rate RX PATH LATENCY1 Full-Duplex Interface Half-Duplex Interface Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 50 MSPS2 RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Temp Full Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C NA Full Full Full Test Level III III III III III III III III III III III III III III III III III NA II V V 15 20 ±1 20 100 10 5 10.5 10.0 80 Min Typ 6.33 8 1.3 400 4.0 53 3.0 2.4 -12 48 1 Monotonic 0.5 35 Max Unit V p-p mV p-p
V
pF MHz nV/rtHz nV/rtHz dB dB dB dB dB MHz dB dB ns ns Bits MSPS Cycles Cycles
Rev. 0 | Page 4 of 48
AD9865
Parameter Signal-to-Noise and Distortion (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 24 dB (Full-Scale =126 mV p-p) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 80 MSPS3 RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output) RxPGA Gain = 40 dB IOUTP± Pins to RX± Pins IOUTG± Pins to RX± Pins RxPGA Gain = 0 dB IOUTP± Pins to RX± Pins IOUTG± Pins to RX± Pins Temp 25°C 25°C 25°C 25°C Full Full Test Level III III III III IV IV 58 Min Typ 43.7 -71 59 -67.2 59 -66 Max Unit dBc dBc dBc dBc dBc dBc
-62.9
25°C 25°C 25°C 25°C 25°C 25°C
III III III III II II 58.9
41.8 -67 58.6 -62.9 59.6 -69.7
dBc dBc dBc dBc dBc dBc
-59.8
25°C 25°C 25°C 25°C
III III III III
83 37 123 77
dBc dBc dBc dBc
1 2
Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC. fIN = 5 MHz, AIN = -1.0 dBFS , LPF cut-off frequency set to 15.5 MHz with Reg. 0x08 = 0x80. 3 fIN = 5 MHz, AIN = -1.0 dBFS , LPF cut-off frequency set to 26 MHz with Reg. 0x08 = 0x80.
POWER SUPPLY SPECIFICATIONS
Table 3. AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V; RSET = 2 k, full-duplex operation with fDATA = 80 MSPS,1 unless otherwise noted
Parameter SUPPLY VOLTAGES AVDD CLKVDD DVDD DRVDD IS_TOTAL (Total Supply Current) POWER CONSUMPTION IAVDD + ICLKVDD (Analog Supply Current) IDVDD + IDRVDD (Digital Supply Current) POWER CONSUMPTION (Half-Duplex Operation with fDATA = 50 MSPS)2 Tx Mode IAVDD + ICLKVDD IDVDD + IDRVDD Rx Mode IAVDD + ICLKVDD IDVDD + IDRVDD Temp Full Full Full Full Full Test Level V V V V II IV IV Min 3.135 3.0 3.0 3.0 Typ 3.3 3.3 3.3 3.3 406 311 95 Max 3.465 3.6 3.6 3.6 475 342 133 Unit V V V V mA mA mA
Full
25°C 25°C 25°C 25°C
IV IV IV IV
112 46 225 36.5
130 49.5 253 39
mA mA mA mA
Rev. 0 | Page 5 of 48
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