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Details, datasheet, quote on part number:AD9870EB
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Datasheet text preview:
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FEATURES 10 MHz300 MHz Input Frequency Baseband (I/Q) Digital Output 10 kHz150 kHz Output Signal Bandwidth 12 dB SSB NF > 1 dBm IIP3 (High IIP3 Mode) 25 dB Continuous AGC Range + 16 dB Gain Step Support for LO and Sampling Clock Synthesis Programmable Decimation Rate, Output Format, AAF Cutoff, AGC and Synthesizer Settings 360 Input Impedance 2.7 V3.6 V Supply Voltage Low Current: 42 mA Typ (High IIP3 Mode), 30 mA Typ (Low IIP3, Fixed Gain Mode) 48-Lead LQFP Package (1.4 mm Thick) APPLICATIONS Portable and Mobile Radio Products Digital UHF/VHF FDMA Products TETRA
IF Digitizing Subsystem AD9870
PRODUCT DESCRIPTION
The AD9870 is a general-purpose IF subsystem that digitizes a low-level 10 MHz300 MHz IF input with a bandwidth of up to 150 kHz. The signal chain of the AD9870 consists of a low-noise amplifier, a mixer, a variable gain amplifier with integral antialias filter, a bandpass sigma-delta analog-to-digital converter, and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit provides the AD9870 with 25 dB of continuous gain adjustment. The high dynamic range of the bandpass sigma-delta converter allows the AD9870 to cope with blocking signals that are as much as 70 dB stronger than the desired signal. Auxiliary blocks include clock and LO synthesizers as well as a serial peripheral interface (SPI) port. The SPI port programs numerous parameters of the AD9870, including the synthesizer divide ratios, the AGC attack and decay times, the AGC target signal level, the decimation factor, the output data format, the 16 dB attenuator, and the bias currents of several blocks. Reducing bias currents allows the user to reduce power consumption at the expense of reduced performance.
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON GCP GCN IF2P IF2N
AD9870
16dB IFIN FREF LO SYNTH SAMP CLOCK SYNTHESIZER LNA VGA / AAF
DAC AGC
- ADC fCLK = 18MHz
DECIMATION FILTER
FORMATTING/SSI
DOUTA DOUTB FS CLKOUT
CONTROL LOGIC VOLTAGE REFERENCE SPI
IOUTC
CLKN
CLKP
VCM
LON
LOP
PC
PD
PE
LO VCO AND LOOP FILTER
CLK VCO AND LOOP FILTER
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
SYNCB
VREFN
VREFP
IOUTL
AD9870SPECIFICATIONS VDDP = 5.0 V, CLK = 18 MSPS, F = 73.35 MHz, F
Parameter OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Digital Supply Voltage (VDDD, VDDC, VDDL) Interface Supply Voltage (VDDH) Charge Pump Supply Voltage (VDDP, VDDQ) Total Current SSB Noise Figure @ Max VGA Gain Input Third-Order Intercept (IIP3) Input Impedance Gain Variation Over Temperature PREAMP + MIXER Maximum Input and LO Frequencies LO SYNTHESIZER LO Input Frequency LO Input Amplitude FREF (Reference) Frequency FREF Input Amplitude Minimum Charge Pump Output Current Maximum Charge Pump Output Current Charge Pump Output Compliance Voltage2 Synthesizer Resolution CLOCK SYNTHESIZER CLK Input Frequency CLK Input Amplitude Minimum Charge Pump Output Current Maximum Charge Pump Output Current Charge Pump Output Compliance Voltage2 Synthesizer Resolution SIGMA-DELTA ADC Resolution Clock Frequency (fCLK) Center Frequency Dynamic Range Passband Gain Variation DECIMATOR Decimation Factor Passband Width Passband Gain Variation Alias Attenuation GAIN CONTROL Programmable Gain Step AGC Gain Range (Continuous) AGC Attack Time SPI PC Clock Frequency PD Hold Time SSI CLKOUT Frequency Output Rise/Fall Time 7.75 0.3 0.1 0.3 Programmable in 0.625 mA Steps Programmable in 0.625 mA Steps 0.25 6.25 13 0.3 Conditions1 Min 2.7 2.7 1.8 2.7 High IIP3 Setting High IIP3 Setting Low IIP3 Setting High IIP3 Setting Low IIP3 Setting
(VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ = IF LO = 71.1 MHz, unless otherwise noted.)
Typ Max Unit
3.0 3.0
3.6 3.6 3.6
V V V V mA dB dB dBm dBm dB MHz
5
3.0 42 12 12 1 10 360 0.6 300
5.5 50.6
300 1.0 25 3 0.625 5.000 VDDP 0.25
MHz V p-p MHz V p-p mA mA V kHz MHz V p-p mA mA V kHz Bits MHz MHz dB dB
18 0.625 5.000
Clock VCO Off Programmable in 0.625 mA Steps Programmable in 0.625 mA Steps
0.25 2.2 16 13 BW = 10 kHz fCLK/8 88
VDDQ 0.25
18 0.5
Programmable in Steps of 60
60 50 85 16 25
960 1 % dB dB dB dB µs MHz ns MHz ns ns ns ns °C °C
Programmable
18 40
60 7000 10
10 1 CMOS Output Mode, Drive Strength = 0 CMOS Output Mode, Drive Strength = 1 CMOS Output Mode, Drive Strength = 2 CMOS Output Mode, Drive Strength = 3 40 40 18 120 45 16 10 +95 +85
OPERATING TEMPERATURE RANGE Basic Functions Meets All Specifications
NOTES 1 Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, 25 pF load on SSI output pins: VDDx = 3.0 V. 2 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
Specifications subject to change without notice.
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AD9870
ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit
VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, IFIN, CXIF, CXVL, CXVM PC, PD, PE, CLKOUT, DOUTA, DOUTB, FS, SYNCB IF2N, IF2P, GCP, GCN VREFP, VREFN, VCM IOUTC IOUTL CLKP, CLKN FREF Junction Temperature Storage Temperature Lead Temperature (10 sec)
GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDS VDDR, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI GNDP, GNDQ GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDQ, GNDP, GNDS GNDI GNDH GNDF GNDA GNDQ GNDP GNDC GNDL
0.3 4.0 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 65
+4.0 +4.0 +6.0 +0.3 VDDI + 0.3 VDDH + 0.3 VDDF + 0.3 VDDA + 0.3 VDDQ + 0.3 VDDP + 0.3 VDDC + 0.3 VDDL + 0.3 150 +150 300
V V V V V V V V V V V V °C °C °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
THERMAL CHARACTERISTICS Thermal Resistance
48-Lead LQFP JA = 91°C/W JC = 28°C/W
ORDERING GUIDE
Model AD9870 AD9870EB
Temperature Range 40°C to +85°C
Package Description 48-Lead Thin Plastic Quad Flatpack (LQFP) Evaluation Board
Package Option ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9870 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9870
PIN CONFIGURATION
IOUTL GNDP CXVM VDDL
48 47 46 45 44 43 42 41 40 39 38 37
MXOP 1 MXON 2 GNDF 3 IF2N 4 IF2P 5 VDDF 6 GCP 7 GCN 8 VDDA 9 GNDA 10 VREFP 11 VREFN 12
VDDP
CXVL
GNDI
VDDI
IFIN CXIF
LON
LOP
PIN 1 IDENTIFIER
36 35 34 33
GNDL FREF GNDS SYNCB GNDH FS DOUTB DOUTA CLKOUT VDDH VDDD PE
AD9870
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
VDDQ IOUTC
PC
GNDQ
VDDC
GNDC
CLKP
VCM
CLKN GNDS
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic Description MXOP MXON GNDF IF2N IF2P VDDF GCP GCN VDDA GNDA VREFP VREFN VCM VDDQ IOUTC GNDQ VDDC GNDC CLKP CLKN GNDS GNDD PC PD Mixer Output, Positive Mixer Output, Negative Ground for VGA Second IF Input (to VGA), Negative Second IF Input (to VGA), Positive Positive Power Supply for Antialias Filter/VGA Filter Capacitor for VGA Gain Control, Positive Filter Capacitor for VGA Gain Control, Negative Positive Power Supply for ADC Ground for ADC Voltage Reference, Positive Voltage Reference, Negative Common-Mode Voltage (Requires 20 k to GNDA) Pos. Power Supply for Clock Synth. Charge Pump Clock Synthesizer Charge Pump Output Current Ground for Clock Synthesizer Charge Pump Positive Power Supply for Clock Synthesizer Ground for Clock Synthesizer Sampling Clock Input/Clock VCO Tank, Positive Sampling Clock Input/Clock VCO Tank, Negative Substrate Ground Ground for Digital Functions Clock Input for SPI Port Data I/O for SPI Port Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Mnemonic PE VDDD VDDH CLKOUT DOUTA DOUTB FS GNDH SYNCB GNDS FREF GNDL GNDP IOUTL VDDP VDDL CXVM LON LOP CXVL GNDI CXIF IFIN VDDI Description Enable Input for SPI Port Positive Power Supply for Internal Digital Functions Positive Power Supply for Digital Interface Clock Output for SSI Port Data Output for SSI Port Data Output for SSI Port, Unused Frame Sync for SSI Port Ground for Digital Interface Resets the SSI and Decimator Counters Substrate Ground Reference Frequency Input for Both Synthesizers Ground for LO Synthesizer Ground for LO Synthesizer Charge Pump LO Synthesizer Charge Pump Output Current Positive Power Supply for LO Synth. Charge Pump Positive Power Supply for LO Synthesizer External Capacitor for Mixer Bias LO Input to Mixer and LO Synthesizer, Negative LO Input to Mixer and LO Synthesizer, Positive External Capacitor for Preamp Power Supply Ground for Mixer and Preamp External Capacitor for Preamp Bias First IF Input (to Preamp) Positive Power Supply for Mixer and Preamp
4
GNDD
PD
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AD9870
SERIAL PERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed below as well as to read back their contents. Table I provides a list of the registers that may be programmed through the SPI port. Addresses and default values are given in hexadecimal form.
Table I. SPI Address Map
Address Bit (Hex) Breakdown Width Default Value Name Description
POWER CONTROL REGISTERS 0x00 0x01 (7:0) (7:6) (5:4) (3:2) (1:0) (7:0) 8 2 2 2 2 8 0xFF 0 0 0 1 0x00 STBY LNAB MIXB CKOB ADCB TEST Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, VGA, ADC). LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA). Mixer Bias Current (0 = 1 mA, 1 = 2 mA, 2 = 3 mA, 3 = 4 mA). CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.53 mA, 3 = 0.85 mA). ADC Amplifier Bias (0 = 2.4 mA, 1 = 3.2 mA, 2 = 4.0 mA, 3 = 4.8 mA). Factory Test Mode.
0x02 AGC 0x03 0x04 0x05 0x06
(7) (6:0) (7:0) (7:4) (3:0) (7:4) (3:0) (2:0)
1 7 8 4 4 4 4 3
0 0x3F 0xFF 0 0 0 0 0
ATTEN Apply 16 dB attenuation in the front end. AGCG(14:8) AGC Gain Setting (7 MSBs of a 15-bit two's-complement word). AGCG(7:0) AGCA AGCD AGCO AGCD AGCR AGC Gain Setting (8 LSBs of a 15-bit two's-complement word). Default corresponds to maximum gain. AGC Attack Time Setting. Default yields 50 Hz raw loop bandwidth. AGC Decay Time Setting. Default is decay time = attack time. AGC Overload Update Setting. Default is slowest update. Fast AGC (Minimizes resistance seen between GCN and GCP). AGC Enable/Reference Level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below clip).
DECIMATION FACTOR 0x07 (3:0) 4 4 M Decimation Factor = 60 × (M + 1). Default is decimate-by-300.
LO SYNTHESIZER 0x08 0x09 0x0A (5:0) (7:0) (7:5) (4:0) (7:0) (6) (5) (4:2) (1:0) (3:0) (7:0) 6 8 3 5 8 1 1 3 2 4 8 0x00 0x38 0x5 0x00 0x1D 0 0 0 0 0x0 0x04 LOR(13:8) LOR(7:0) LOA LOB(12:8) LOB(7:0) LOF LOINV LOI LOTM LOFA(13:8) LOFA(7:0) Reference Frequency Divisor (6 MSBs of a 14-Bit Word). Reference Frequency Divisor (8 LSBs of a 14-Bit Word). Default (56) Yields 300 kHz from fREF = 16.8 MHz. "A" Counter (Prescaler Control Counter). "B" Counter MSBs (5 MSBs of a 13-Bit Word). Default LOA and LOB Values Yield 300 kHz from 73.35 MHz2.25 MHz. "B" Counter LSBs (8 LSBs of a 13-Bit Word). Enable Fast Acquire. Invert Charge Pump (0 = Pump_Up IOUTL Sources Current). Charge Pump Current in Normal Operation. IPUMP = (LOI + 1) × 0.625 mA. Manual Control of LO Charge Pump (3 = Off, 2 = Down, 1 = Up, 0 = Normal). LO Fast Acquire Time Unit (4 MSBs of a 14-Bit Word). LO Fast Acquire Time Unit (8 LSBs of a 14-Bit Word).
0x0B 0x0C
0x0D 0x0E
CLOCK SYNTHESIZER 0x10 0x11 (5:0) (7:0) 6 8 00 0x38 CKR(13:8) CKR(7:0) Reference Frequency Divisor (6 MSBs of a 14-Bit Word). Reference Frequency Divisor (8 LSBs of a 14-Bit Word). Default Yields 300 kHz from fREF =16.8 MHz. Min = 3, Max = 16383. Synthesized Frequency Divisor (5 MSBs of a 13-Bit Word).
0x12
(4:0)
5
0x00
CKN(12:8)
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