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Details, datasheet, quote on part number:AD9873-EB
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| Part: | AD9873-EB |
| Category: | Multimedia => Video => TV Applications => Function Block |
| Description: | Analog Front End Converter For Set-top Box, Cable Modem, And Other Broadband Communication Applications |
| Company: | Analog Devices |
| Datasheet: | Download AD9873-EB datasheet File size : 958 kB |
| Request For quote: | Find where to buy AD9873-EB
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Datasheet text preview:
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FEATURES Low-Cost 3.3 V CMOS Analog Front End Converter for MCNS-DOCSIS, DVB, DAVIC-Compliant Set-Top Box, Cable Modem Applications 232 MHz Quadrature Digital Upconverter DC to 65 MHz Output Bandwidth 12-Bit Direct IF D/A Converter (TxDAC+ ®) Programmable Reference Clock Multiplier (PLL) Direct Digital Synthesis Interpolator SIN(x)/x Compensation Filter Four Programmable, Pin-Selectable Modulator Profiles Single-Tone Mode for Frequency Synthesis Applications 12-Bit, 33 MSPS Sampling Direct IF A/D Converter with Auxiliary Automatic Clamp Video Input Multiplexer 10-Bit, 33 MSPS Sampling Direct IF A/D Converter Dual 8-Bit, 16.5 MSPS Sampling IQ A/D Converter Two Independently Programmable Sigma-Delta Converters Direct Interface to AD8321/AD8323 PGA Cable Driver Programmable Frequency Output Power-Down Modes APPLICATIONS Cable and Satellite Systems PC Multimedia Digital Communications Data and Video Modems Cable Modem Set-Top Boxes Powerline Modem Broadband Wireless Communication GENERAL DESCRIPTION
Analog Front End Converter for Set-Top Box, Cable Modem AD9873
FUNCTIONAL BLOCK DIAGRAM
AD9873
COS Tx IQ Tx Tx SYNC INTERPOLATOR FILTER SIN 3 PLL SERIAL ITF PROFILE 4 2 CONTROL FUNCTIONS DDS 12 12 CA INV SINC 12 DAC Tx
SDELTA0 SDELTA1 REF CLK
8
ADC
IIN
Rx IQ Rx IF Rx SYNC
8 Rx 10
ADC
QIN
ADC
IF10
12
IF12 ADC MUX VIDEO
Th e AD9873 integrates a complete 232 MHz quadrature digital transmitter and a multichannel receiver with four highperformance analog-to-digital converters (ADC) for various video and digital data signals. The AD9873 is designed for cable modem set-top box applications, where cost, size, power dissipation, and dynamic performance are critical attributes. A single external crystal is used to control all internal conversion and data processing cycles. The transmit section of the AD9873 includes a high-speed direct digital synthesizer (DDS), a high-performance, high-speed 12-bit digital-to-analog converter (DAC), programmable clock m u l t i p l i e r circuitry, digital filters, and other digital signal processing functions, to form a complete quadrature digital up-converter device.
TxDAC+ is a registered trademark of Analog Devices, Inc.
On the receiver side, two 8-bit ADCs are optimized for IQ demodulated "out-of band" signals. An on-chip 10-bit ADC is typically used as a direct IF input of 256 QAM modulated signals in cable modem applications. A second direct IF input and an auxiliary video input with automatic programmable clamp function are multiplexed to a high-performance 12-bit video ADC. The chip's programmable sigma-delta modulated outputs and an output clock may be used to control external components such as programmable gain amplifiers (PGA) and mixer stages. Three pins provide a direct interface to the AD8321/AD8323 programmable gain amplifier (PGA) cable driver. The AD9873 is available in a space-saving 100-lead MQFP package.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD9873
TABLE OF CONTENTS Page Page
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 7 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 7 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 7 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DEFINITIONS OF TERMS . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . 10 REGISTER BIT DEFINITIONS . . . . . . . . . . . . . . . . . . . 12 TYPICAL PERFORMANCE CHARACTERISTICS . . . 14 Typical Power Consumption Characteristics . . . . . . . . . 14 Dual Sideband Transmit Spectrum . . . . . . . . . . . . . . . . 14 Single Sideband Transmit Spectrum . . . . . . . . . . . . . . . 15 Typical QAM Transmit Performance Characteristics . . 16 Typical ADC Performance Characteristics . . . . . . . . . . . 18 THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . 20 Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 OSC IN Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . 21 Receive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CLOCK AND OSCILLATOR CIRCUITRY . . . . . . . . . . 22 PROGRAMMABLE CLOCK OUTPUT REF CLK . . . . 23 SIGMA-DELTA OUTPUTS . . . . . . . . . . . . . . . . . . . . . . 23 SERIAL INTERFACE FOR REGISTER CONTROL . . . 23 General Operation of the Serial Interface . . . . . . . . . . . . 23 Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial Interface Port Pin Description . . . . . . . . . . . . . . . 24 MSB/LSB Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . 24
TRANSMIT PATH (Tx) . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half-Band Filters (HBFs) . . . . . . . . . . . . . . . . . . . . . . . Cascaded Integrator--COMB (CIC) Filter . . . . . . . . . . Combined Filter Response . . . . . . . . . . . . . . . . . . . . . . . Inverse SINC Filter (ISF) . . . . . . . . . . . . . . . . . . . . . . . Tx Signal Level Considerations . . . . . . . . . . . . . . . . . . . Tx Throughput and Latency . . . . . . . . . . . . . . . . . . . . . D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROGRAMMING/WRITING THE AD8321/AD8323 CABLE DRIVER AMPLIFIER GAIN CONTROL . . . RECEIVE PATH (Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving the Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . Op Amp Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . ADC Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage References . . . . . . . . . . . . . . . . . . . . . . . . Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER AND GROUNDING CONSIDERATIONS . . . EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . .
24 24 24 25 25 25 27 28 28 28 29 30 30 30 30 31 31 31 31 32 33 33 33 39
2
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SPECIFICATIONS
Parameter
(VAS = 3.3 V 5%, VDS = 3.3 V 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8, N = 4), ADC Sample Rate derived from PLL fMCLK , RSET = 10 k , 75 DAC Load)
Temp Full Full 25 C 25 C 25 C 25 C N/A Full 25 C 25 C 25°C 25 C 25 C 25 C 25 C Full 25 C 25 C 25 C Full Full Full Full N/A Full N/A 25 C 25 C 25 C 25 C Full Full Full 25 C 25 C 25 C 25 C 25 C 25 C 25 C Full Test Level III III III IV IV IV N/A III I I I IV IV IV IV III IV IV IV III III III III N/A III N/A IV IV IV IV IV IV IV IV IV IV IV IV IV I II 43.5 50 3 35 Min Typ Max 232 33 65
AD9873
Unit MHz MHz % pF M ps rms Bits mA % FS % FS V LSB LSB pF dBc/Hz V dBc dBc dBc dB dB dB dB Bits MHz ADC Cycles LSB LSB % FSR % FSR LSB LSB V p-p pF k ns ps rms MHz µV
SYSTEM CLOCK, DAC SAMPLING fSYSCLK Frequency Range OSC IN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Capacitance Input Resistance MCLK OUT JITTER (fMCLK Derived from PLL) TxDAC CHARACTERISTICS Resolution Full-Scale Output Current Gain Error (Using Internal Reference) Output Offset Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 4 mA 65 MHz Analog Out, IOUT = 4 mA Narrowband SFDR ( 100 kHz Window) 65 MHz Analog Out, IOUT = 4 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass Band Amplitude Ripple (f fIQCLK × 3/4) 8-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error for Each 8-Bit ADC Gain Error for Each 8-Bit ADC Offset Matching Between 8-Bit ADCs Gain Matching Between 8-Bit ADCs Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (3 dB) Input Referred Noise Reference Voltage Error REFT8REFB8 (0.5 V) Dynamic Performance (AIN = 0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD)
1
50 3 100 6 12 4 0.14 1.23 ± 2.5 ±8 5 113
2 3 1 1.18
20 +3 +1 1.28
0.5 59 54 79 55
+1.5
0.1 0.5 63 8 16.5 3.5 0.5 0.5 0.75 4 3 4.5 1 1.4 4 2.0 1.2 90 600 ±4 48 ± 92
mV dB
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3
AD9873SPECIFICATIONS
Parameter 8-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (AIN = 0.5 dB FS, f = 5 MHz) Effective Number of Bits (ENOB) Effective Number of Bits (ENOB)2 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain 10-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (3 dB) Input Referred Noise Reference Voltage REFT10REFB10 (1 V) Dynamic Performance (AIN = 0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) Effective Number of Bits (ENOB) Effective Number of Bits (ENOB)3 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain 12-BIT ADC CHARACTERISTICS Resolution Conversion Rate Pipeline Delay DC Accuracy Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Analog Input Input Voltage Range Input Capacitance Differential Input Resistance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (3 dB) Input Referred Noise Reference Voltage REFT12REFB12 (1 V) Temp Test Level Min Typ Max Unit Full Full Full Full Full 25 C 25 C N/A Full N/A 25 25 25 25 C C C C II IV II II II IV IV N/A III N/A IV IV IV IV IV IV IV IV IV IV IV I II II IV II II II IV IV N/A III N/A IV IV IV IV IV IV IV IV IV IV IV I 57.9 9.3 58.2 65.7 6.9 43.5 58 7.68 7.68 48 66 64 <0.1 1 10 33 5.5 0.75 0.5 0.5 3 2 1.4 4 2.0 1.2 95 350 ±6 60.1 9.7 9.8 60.1 75.8 80 <0.1 <1 12 33 5.5 0.75 1.5 1 2 2 1.4 4 2.0 1.2 85 75 ±6 ± 200 ± 200 Bits Bits dB dB dB Degree LSB Bits MHz ADC Cycles LSB LSB % FSR % FSR V p-p pF k ns ps rms MHz µV mV dB Bits Bits dB dB dB Degree LSB Bits MHz ADC Cycles LSB LSB % FSR % FSR V p-p pF k ns ps rms MHz µV mV
57
Full 25 C 25 C 25 C 25 C 25 C 25 C 25 C Full Full Full Full Full Full 25 C 25 C N/A Full N/A 25 25 25 25 C C C C
63.9
Full 25 C 25 C 25 C 25 C 25 C 25 C 25 C
4
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AD9873
Parameter 12-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (AIN = 0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) Signal-to-Noise and Distortion Ratio (SINAD)3 Effective Number of Bits (ENOB) Effective Number of Bits (ENOB)3 Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD) Total Harmonic Distortion (THD)3 Spurious Free Dynamic Range (SFDR) Spurious Free Dynamic Range (SFDR)3 Differential Phase Differential Gain VIDEO CLAMP INPUT Input Voltage Range Clamp Current Positive Clamp Droop Current Clamp Level Offset Programming Range Clamp Level Resolution Carrier Rejection Filter Bandwidth (3 dB) Dynamic Performance (AIN = 0.5 dB FS, f = 5 MHz) Signal-to-Noise and Distortion Ratio (SINAD) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Differential Phase Differential Gain CHANNEL-TO-CHANNEL ISOLATION Tx DAC-to-ADC Isolation (5 MHz Analog Output) Isolation Between Tx and 8-Bit ADCs Isolation Between Tx and 10-Bit ADC Isolation Between Tx and 12-Bit ADC ADC-to-ADC Isolation (AIN = 0.5 dB FS, f = 5 MHz) Isolation Between IF12 and Video Isolation Between IF10 and IF12 Isolation Between Q in and IF10 Isolation Between Q in and I Inputs TIMING CHARACTERISTICS (20 pF Load) Wake-Up Time Minimum RESET Pulsewidth Low (tRL) Digital Output Rise/Fall Time Tx/Rx Interface MCLK Frequency (fMCLK) TxSYNC/TxIQ Set Up Time (tSU) TxSYNC/TxIQ Hold Time (tHD) RxSYNC/RxIQ/IF to Valid Time (tTV) RxSYNC/RxIQ/IF Hold Time (tHT) Serial Control Bus SCLK Frequency (fSCLK) Clock Pulsewidth High (tPWH) Clock Pulsewidth Low (tPWL) Clock Rise/Fall Time Data/Chip-Select Setup Time (tDS) Data Hold Time (tDH) Data Valid Time (tDV) REV. 0 Temp Test Level Min Typ Max Unit
Full Full Full Full Full Full Full Full Full Full 25 C 25 C Full 25 C 25 C 25 C 25 C 25 C Full Full Full Full Full 25°C 25°C
III IV III IV III IV III IV III IV IV IV IV IV IV III IV IV IV IV IV IV IV IV IV
62.3 10.0 63.3
65.7
65 67.4 10.5 10.8 65.3 67.4 77.6 77.6 80 80 <0.1 <1 2 1.3 2 512 16 0.6 52 8.34 61.0 53.0 55.0 <0.1 <8
65.4
dB dB Bits Bits dB dB dB dB dB dB Degree LSB V mA A LSB LSB MHz dB Bits dB dB dB Degree LSB
256
2032
25 C 25 C 25 C 25 25 25 25 C C C C
IV IV IV
>80 >85 >90
dB dB dB
III IV IV IV N/A N/A III III III III III III III III III III III III III
70
>70 >80 >80 >70 200 5
dB dB dB dB tMCLK Cycles tMCLK Cycles ns MHz ns ns ns ns MHz ns ns ms ns ns ns
N/A N/A 25 C 25 25 25 25 25 C C C C C
2.8
4 66
3 3 5.2 0.2 15 30 30 1 25 0 30
Full Full Full Full Full Full Full 5
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