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Details, datasheet, quote on part number:AD9874EB
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Datasheet text preview:
PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 10-300 MHz Input Frequency Baseband (I/Q) Digital Output 10-270 kHz Output Signal Bandwidth 8.7 dB SSB NF (typ.) +1.1 dBm IIP3 (typ.; max. bias) AGCFree Range up to -28 dBm 12 dB Continuous AGC Range 16 dB Front End Attenuator LO and Sampling Clock Synthesizers Programmable decimation factor, output format, AGC and synthesizer settings 370 Input Impedance 2.7-3.6 V Supply Voltage Low Current: 22 mA (typ., max. bias) 48-Pin LQFP package (1.4mm thick) APPLICATIONS Portable and Mobile Radio Products Digital UHF/VHF FDMA products TETRA, APCO25, GSM/EDGE
IF Digitizing Subsystem AD9874
P R O D U C T DESCRIPTION The AD9874 is a general-purpose IF subsystem which digitizes a
low-level 10-300 MHz IF input with a bandwidth up to 270 kHz. The signal chain of the AD9874 consists of a low-noise amplifier, a mixer, a bandpass sigma-delta analog-to-digital converter and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high dynamic range and inherent anti-aliasing provided by the bandpass sigma-delta converter allow the AD9874 to cope with blocking signals 80 dB stronger than the desired signal. Auxiliary blocks include clock and LO synthesizers as well as a serial peripheral interface (SPI) port. The SPI port programs numerous parameters of the AD9874, including the synthesizer divide ratios; the AGC attenuation, attack time, decay time and target signal level; the decimation factor; the output data format; the 16 dB attenuator; as well as selected bias currents. Reducing bias currents allows the user to reduce power consumption at the expense of reduced performance.
FUNCTIONAL BLOCK DIAGRAM
MXO P MXO N I F2 P I F2 N G CP GCN
AD9874
-16dB
IFIN L NA ADC
DAC AGC
Decimation Filter
Formatting/SSI
DOUTA DOUTB FS CLKOUT
FREF
fCLK= 13-26MHz
Control Logic
LO Synth.
Sample Clock Synthesizer
Voltage Reference
SPI
IO UTL
IO UTC
LO N
CLKN
CLKP
LO P
VREFP
V RE F N
PC
PD
PE
LO VCO & Loop Filter
CLK VCO & Loop Filter
REV. P r B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002
S Y NC B
V CM
PRELIMINARY TECHNICAL DATA
= 3.0 V, VDDC VDDL = 3.0 VDDH = 3.0 V, VDDQ AD9874SPECIFICATIONS(FVDD=I =18VDDF =FVDDA109.65 MHz, F ==107.4 MHz, FV, VDDD =MHz,unless otherwise=VDDP = 5.0 V, MSPS, = = 16.8 noted)
CLK IF LO REF 1
Parameter SYSTEM DYNAMIC PERFORMANCE SSB Noise Figure @ Min VGA Attenuation3,4 @ Max VGA Attenuation 3,4 Dynamic Range w/ AGC Enabled3,4 IF Input Clip Point @ Max VGA Attenuation3 @ Min VGA Attenuation 3 Input Third-Order Intercept (IIP3) Gain Variation Over Temperature LNA + MIXER Maximum RF and LO Frequency Range LNA Input Impedance Mixer LO Drive Level Mixer LO Input Resistance LO SYNTHESIZER LO Input Frequency LO Input Amplitude FREF (Reference) Frequency FREF Input Amplitude Minimum Charge Pump Output Current5 Maximum Charge Pump Output Current5 Charge Pump Output Compliance Voltage6 Synthesizer Resolution CLOCK SYNTHESIZER CLK Input Frequency CLK Input Amplitude Minimum Charge Pump Output Current5 Maximum Charge Pump Output Current5 Charge Pump Output Compliance Voltage6 Synthesizer Resolution SIGMA-DELTA ADC R esolution Clock Frequency (fCLK) Center Frequency Passband Gain Variation Alias Attenuation GAIN CONTROL Programmable Gain Step AGC Gain Range (Continuous) AGC Attack Time (Programmable) OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Digital Supply Voltage (VDDD, VDDC, VDDL) Interface Supply Voltage8 (VDDH) Charge Pump Supply Voltage (VDDP, VDDQ) Total Current High Performance Setting Low Power Mode Standby OPERATING TEMPERATURE RANGE Basic Functions Meets All Specifications
NOTES
2
Temp Full Full Full Full Full Full Full Full 25 o C Full 25 o C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Test Level IV IV IV IV IV IV IV IV V IV V IV IV IV VI VI VI VI IV IV IV VI VI VI IV IV VI IV IV IV VI VI IV
Min
Typ 8.7 TBD 92 -18 -30 0 TBD 300 370//1.4
Max
Unit dB dB dB dBm dBm dBm dB MHz //pF Vp.p. k MHz V p-p 25 MHz V p-p mA mA V kHz MHz V p-p mA mA V kHz Bits MHz MHz dB dB dB dB µs
0.30 1 7.75 0.3 0.1 0.3 0.625 5.000 0.25 6.25 13 0.3 0.625 5.000 0.25 2.2 16 13 f C L K/ 8 80 16 12 40
1
300 1.0 3 VDDP 0.25
26 VDDC VDDQ 0.25
24 26 0.5
7000
Full Full Full Full Full Full Full
VI VI VI VI VI VI VI
2.7 2.7 1.8 2.7
3.0 3.0
3.6 3.6 3.6
V V V V mA mA mA
3.0 22 18 0.1
5.5
40 30
+85 +85
°C °C
1 Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, decimation fator = 900, 16-bit Digital Output, 25 pF load on SSI output pins . 2 Includes 0.9 dB Loss of Matching Network 3 AGC w/ DVGA enabled, 4 Measured in 10 kHz bandwidth 5 Programmable in 0.625 mA Steps 6 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). 7 Clock VCO Off
8 VDDH must be less than VDDD + 0.5 V
Specifications subject to change without notice.
2
REV. PrB
PRELIMINARY TECHNICAL DATA
= VDDA = 3.0 V, = VDDL = VDDH = 3.0 V, VDDQ DIGITAL SPECIFICATIONS (VVDDDDPI = VDDFV,=CLK = 18 MSPS, VDDC109.65 MHz,3.0 V,=VDDD =MHz, unless otherwise=noted) 5.0 F= F 107.4
IF LO 1
Parameter DECIMATOR Decimation Factor2 Passband Width Passband Gain Variation Alias Attenuation SPI-READ OPERATION (see figure 1a) PC Clock Frequency PC Clock Period (tCLK) PC Clock HI (tHI) PC Clock LOW (tLOW) PD Set-up Time (tDS) PD Hold Time (tDH) PE Set-up Time (tS) PE Hold Time (tH) SPI-WRITE OPERATION (see figure 1b) PC Clock Frequency PC Clock Period (tCLK) PC Clock HI (tHI) PC Clock LOW (tLOW) PD Set-up Time (tDS) PD Hold Time (tDH) PD Data Valid Time (tDV) PD Output Valid to Hi-Z (tEZ) PE Set-up Time (tS) SSI (see figure 2b) CLKOUT Frequency CLKOUT Period (tCLK) CLKOUT HI (tHI) CLKOUT LOW (tLOW) FS Valid Time (tV) DOUT Data Valid Time(tDV)Full
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Test Level IV IV IV IV I I V V V V V V I I V V V V V V V
Min 48
Typ
Max 960
Unit
50% 1.2 88 10 100 TBD TBD TBD TBD TBD TBD 10 100 TBD TBD TBD TBD TBD TBD TBD
fCLKOUT dB dB MHz ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns
Full Full Full Full Full
IV VI V V V V
f C L K/ 1 5 TBD TBD TBD TBD
fCLK 38.4
ns ns ns ns ns
1 Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, fCLK = 18 MHz, decimation fator = 300, 25 pF load on SSI output pins: VDDx = 3.0 V. 2. Programmable in Steps of 48 or 60 3. CMOS Output Mode w/ CLOAD= 25pF
REV. PrB
3
PRELIMINARY TECHNICAL DATA AD9874
ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit
VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, IFIN, CXIF, CXVL, CXVM PC, PD, PE, CLKOUT, DOUTA, DOUTB, FS, SYNCB IF2N, IF2P, GCP, GCN VREFP, VREFN, RREF IOUTC IOUTL CLKP, CLKN FREF Junction Temperature Storage Temperature Lead Temperature (10 sec)
GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDS VDDR, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI GNDP, GNDQ GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDQ, GNDP, GNDS GNDI GNDH GNDF GNDA GNDQ GNDP GNDC GNDL
0.3 4.0 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 65
+4.0 +4.0 +6.0 +0.3 VDDI + 0.3 VDDH + 0.3 VDDF + 0.3 VDDA + 0.3 VDDQ + 0.3 VDDP + 0.3 VDDC + 0.3 VDDL + 0.3 150 +150 300
V V V V V V V V V V V V °C °C °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
THERMAL CHARACTERISTICS T h e r m a l Resistance
48-Lead LQFP JA = 91°C/W JC = 28°C/W
EXPLANATION OF TEST LEVELS TEST LEVEL
I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. AC testing done on sample basis. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25°C; guaranteed by design and characterization for industrial temperature range.
ORDERING GUIDE
Model AD9874 AD9874EB
Temperature Range 40°C to +85°C
Package Description 48-Lead Thin Plastic Quad Flatpack (LQFP) Evaluation Board
Package Option ST-48
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. PrB
PRELIMINARY TECHNICAL DATA AD9874
PIN CONFIGURATION
VDDI IF IN CXIF GNDI CXVL LOP LON CXVM VDDL VDDP IOUTL GNDP
48 47 46 45 44 43 42 41 40 39 38 37
MXOP 1 MXON 2 GNDF 3 IF2N 4 IF2P 5 VDDF 6 GCP
7
PIN 1 IDENTIFIER
36 35 34 33
GNDL FREF GNDS SYNCB GNDH FS DOUTB DOUTA CLKOUT VDDH VDDD PE
AD9874
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
GCN 8 VDDA 9 GNDA 10 VREFP 11 VREFN 12
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic Description MXOP MXON GNDF IF2N IF2P VDDF GCP GCN VDDA GNDA VREFP VREFN RREF VDDQ IOUTC GNDQ VDDC GNDC CLKP CLKN GNDS GNDD PC PD Mixer Output, Positive Mixer Output, Negative Ground for Front End of ADC Second IF Input (to ADC), Negative Second IF Input (to ADC), Positive Positive Power Supply for Front End of ADC Filter Capacitor for ADC Full-Scale Control Full-Scale Control Ground Positive Power Supply for ADC Back End Ground for ADC Back End Voltage Reference, Positive Voltage Reference, Negative Reference Resistor: Requires 100k to GNDA Pos. Power Supply for Clock Synth. Charge Pump Clock Synthesizer Charge Pump Output Current Ground for Clock Synthesizer Charge Pump Positive Power Supply for Clock Synthesizer Ground for Clock Synthesizer Sampling Clock Input/Clock VCO tank, Positive Sampling Clock Input/Clock VCO tank, Negative Substrate Ground Ground for Digital Functions Clock Input for SPI port Data I/O for SPI Port Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Mnemonic PE VDDD VDDH CLKOUT DOUTA DOUTB FS GNDH SYNCB GNDS FREF GNDL GNDP IOUTL VDDP VDDL CXVM LON LOP CXVL GNDI CXIF IFIN VDDI Description Enable Input for SPI Port Positive Power Supply for Internal Digital Functions Positive Power Supply for Digital Interface Clock Output for SSI Port Data Output for SSI Port Data Output for SSI Port, Inverted Frame Sync for SSI Port Ground for Digital Interface Resets SSI and Decimator Counters; Active Low Substrate Ground Reference Frequency Input for Both Synthesizers Ground for LO Synthesizer Ground for LO Synthesizer Charge Pump LO Synthesizer Charge Pump Output Current Positive Power Supply for LO Synth. Charge Pump Positive Power Supply for LO Synthesizer External Filter Capacitor; DC Output of LNA LO Input to Mixer and LO Synthesizer, Negative LO Input to Mixer and LO Synthesizer, Positive External Bypass Capacitor for LNA Power Supply Ground for Mixer and LNA External Capacitor for Mixer V-I Converter Bias First IF Input (to LNA) Positive Power Supply for LNA and Mixer
REV. PrB
VDDQ IOUTC GNDQ V DDC GNDC CL KP CLKN G NDS GNDD PC PD
RREF
5
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