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Details, datasheet, quote on part number:ADC912AFP
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Datasheet text preview:
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FEATURES Low Cost Low Transition Noise between Code 12-Bit Accurate 1/2 LSB Nonlinearity Error over Temperature No Missing Codes at All Temperatures 10 s Conversion Time Internal or External Clock 8- or 16-Bit Data Bus Compatible Improved ESD Resistant Design Latchup Resistant Epi-CMOS Processing Low 95 mW Power Consumption Space-Saving 24-Lead 0.3" DIP, or 24-Lead SOIC APPLICATIONS Data Acquisition Systems DSP System Front End Process Control Systems Portable Instrumentation GENERAL DESCRIPTION
CMOS Microprocessor-Compatible 12-Bit A/D Converter ADC912A
FUNCTIONAL BLOCK DIAGRAM
AGND VREFIN 4 12-BIT DAC 5k AIN VDD VSS
ADC912A
SUCCESSIVE APPROXIMATION REGISTER
12-BIT LATCH 8 CONTROL LOGIC
BUSY CS RD HBEN
MULTIPLEXER 8 THREE-STATE OUTPUT DRIVERS THREE-STATE OUTPUT DRIVERS CLOCK OSCILLATOR
CLK OUT CLK IN
D11 D8
D7 D4 DGND D3/11 D0/8
The ADC912A is a monolithic 12-bit accurate CMOS A/D converter. It contains a complete successive-approximation A/D converter built with a high-accuracy D/A converter, a precision bipolar transistor high-speed comparator, and successiveap proximation logic including three-state bus interface for logic compatibility. The accuracy of the ADC912A results from the addition of precision bipolar transistors to Analog Devices' advanced-oxide isolated silicon-gate CMOS process. Particular attention was paid to the reduction of transition noise between adjacent codes achieving a 1/6 LSB uncertainty. The low noise design produces the same digital output for dc analog inputs
256
not located at a transition voltage, see Figures 1 and 2. NPN digital output transistors provide excellent bus interface timing, 125 ns access and bus disconnect time which results in faster data transfer without the need for wait states. An external 1.25 MHz clock provides a 10 µs conversion time. In stand-alone applications an internal clock can be used with external crystal. An external negative five-volt reference sets the 0 V to 10 V input range. Plus 5 V and minus 12 V power supplies result in 95 mW of total power consumption.
NUMBER OF OCCURRENCES
192
128
64
DIGITAL OUTPUT
10 0%
256 SUCCESSIVE CONVERSIONS WITH AIN = 4.99756V
100 90
TRANSITION NOISE
0 2045 2046 2047 2048 2049 OUTPUT CODE Decimal
ANALOG INPUT
Figure 1. Code Repetition
Figure 2. Transition Noise Cross Plot
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001
(VDD = +5 V 5%, VSS = 11.4 V to 15.75 V, VREFIN = 5 V, Analog Input O V to 10 V; External fCLK = 1.25 MHz; 40 C to +85 C applies to ADC912A/F unless otherwise noted.)
Parameter STATIC ACCURACY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Full-Scale Tempco1 ANALOG INPUT Input Voltage Range Input Current Range POWER SUPPLIES Positive Supply Current Negative Supply Current Power Consumption Power Supply Rejection Ratio DIGITAL INPUTS Logic Input High Voltage Logic Input Low Voltage Logic Input Current Digital Input Capacitance DIGITAL OUTPUTS Logic Input High Voltage Logic Input Low Voltage Three-State Output Leakage Digital Input Capacitance DYNAMIC PERFORMANCE Conversion Time Symbol INL DNL VZSE GFSE TCGFS VIN IIN I DD IS S PD I S S PSRR+ PSRR VINH VINL IIN CIN V OH V OL IO Z CO U T TC VDD = +5 V2 VSS = 12 V2 VDD = +5 V2, VSS = 12 V2 VDD = ± 5%, AIN = 10 V VSS = ± 5%, AIN = 10 V CS, RD, HBEN CS, RD, HBEN CS, RD, HBEN Digital Inputs, CS, RD, HBEN, CLKIN ISOURCE = 0.2 mA ISINK = 1.6 mA D 1 1 D0 / 8 D 1 1 D0 / 8 1 fCLK = 1.25 MHz3 Synchronous Clock Asynchronous Clock 2.4 0.8 ±1 10 Conditions Min 1 1 5 6 5 0 0 5 3 70 1/2 1/2 Typ Max +1 +1 +5 +6 15 10 3 7 5 95 4 4 Unit LSB LSB LSB LSB p p m /° C V mA mA mA mW LSB LSB V V µA pF V V µA pF
ADC912ASPECIFICATIONS
VDD = +5 V, VSS = 12 V VDD = +5 V, VSS = 12 V
7 4
8
0.4 10 15
10.4
10.4 11.2
µs µs
NOTES 1 Guaranteed by design. 2 Converter inactive; CS, RD = High, A IN = 10 V. 3 See Synchronizing Start Conversion information in Converter Operation Details. Typicals (typ) are median values measured at 25 °C. See Typical Performance Characteristics for additional information. Specifications subject to change without notice.
5V 3k D DBN 3k DGND A. HIGH-Z TO V OH (t3) AND VOL TO V OH (t6) CL DBN CL GND B. HIGH-Z TO VOL (t3) AND V OH TO VOL (t6)
5V 3k D DBN 3k DGND A. VOH TO HIGH-Z 10pF DBN 10pF GND B. VOL TO HIGH-Z
Figure 3. Load Circuits for Access Time
Figure 4. Load Circuits for Output Float Delay
2
REV. B
ADC912A
(VDD = +5 V 5%, VSS = 11.4 V to 15.75 V, VREFIN = 5 V, Analog Input 0 V to 10 V; External fCLK = 1.25 MHz; 40 C to +85 C applies to ADC912A/F unless otherwise noted. See Figures 5 to 8.)
Parameter CS to RD Setup Time RD to BUSY Propagation Delay Data Access Time after READ Read Pulsewidth CS to RD Hold Time New Data Valid after BUSY Bus Disconnect Time HBEN to RD Setup Time HBEN to RD Hold Time Delay between Successive Read Operations Symbol t1 t2 t3 3 t4 3 t5 t6 3 t7 t8 t9 t1 0 Conditions Min 0 CL = 100 pF 90 0 CL = 100 pF 20 20 20 350 30 60 0 90 65 150 125 Typ Max Unit ns ns ns ns ns ns ns ns ns ns
TIMING CHARACTERISTICS1, 2
250
NOTES 1 Guaranteed by design. 2 All input control signals are specified with t R = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 3 t3, t4, and t6 are measured with the load circuits of Figure 3 and timed for and output to cross 0.8 V or 2.4 V. 4 t7 is the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 4. Specifications subject to change without notice.
CS
TIMING DIAGRAMS
CS
RD
t1
t5 t4 t2
t1 t4
t5
t1
RD
t5 t10 tCONV t6
OLD DATA DB11 DB0 D10 D9 D8 D7
t1
BUSY
tCONV t7
OLD DATA DB11 DB0
t2 t3
tCONV
t2
BUSY
t3
DATA
t7
NEW DATA DB11 DB0
t3
DATA DATA D OUTPUTS 11
t7
NEW DATA DB11 DB0 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
DATA D OUTPUTS 11
D10
D9
D8
D7
D6
D5
D4
D3/11 D2/10 D1/9 D0/8
FIRST READ DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (OLD DATA) SECOND DB DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1 0 READ
READ DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 5. Parallel Read Timing Diagram, Slow-Memory Mode (HBEN = LOW)
Figure 7. Parallel Read Timing Diagram, ROM Mode (HBEN = LOW)
HBEN
t8
HBEN
CS
t9
t8
t9
t8
t9
t8
CS
t9 t5 t10 t7 t6
OLD DATA DB7 DB0 NEW DATA DB7 DB0
t8
t9
RD
t1 t4 t2
BUSY
t5
t1 t4
t5
t1 t4 t10 t2
t5
t1
RD
t1 t4
t5
tCONV t3 t7
OLD DATA DB7 DB0
t2
BUSY
tCONV
t3
t7
NEW DATA DB11 DB8
t3
t7
NEW DATA DB7 DB0
t3
DATA
t3
t7
DATA
NEW DATA DB11 DB8 D3/11 DB3 DB11 D2/10 DB2 DB10 D1/9 DB1 DB9 D0/8 DB0 DB8
DATA OUTPUTS FIRST READ SECOND READ
D7 DB7 LOW
D6 DB6 LOW
D5 DB5 LOW
D4 DB4 LOW
DATA OUTPUTS FIRST READ (OLD DATA) SECOND READ THIRD READ
D7 DB7 LOW DB7
D6 DB6 LOW DB6
D5 DB5 LOW DB5
D4 DB4 LOW DB4
D3/11 DB3 DB11 DB3
D2/10 DB2 DB10 DB2
D1/9 DB1 DB9 DB1
D0/8 DB0 DB8 DB0
Figure 6. Two-Byte Read Timing Diagram, Slow-Memory Mode
Figure 8. Two-Byte Read Timing Diagram, ROM Mode
REV. B
3
ADC912A
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 7 V VREFIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD AGND to DGND . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . 15 V to +15 V Digital Input Voltage to DGND, Pins 17, 1921 . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Digital Output Voltage to DGND, Pins 411, 1316, 18, 22 . . . . . . . . . 0.3 V to VDD + 0.3 V
Operating Temperature Range Extended Industrial: ADC912A/F . . . . . . . 40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Package Power Dissipation . . . . . . . . . . . . . . (TJ maxTA)/JA Thermal Resistance JA Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W SOIC-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 °C
ORDERING GUIDE
Model ADC912AFP ADC912AFS
Temperature Range 40°C to +85°C 40°C to +85°C
INL (LSB) ±1 ±1
Package Description 24-Lead Narrow-Body Plastic 24-Lead Wide-Body SOIC
Package Option N-24 R-24
Table I. Analog Input to Digital Output Code Conversion
Analog Input Voltage 0 V to 10 V 10 V to +10 V +FS 1 LSB +FS 1 1/2 LSB Midscale + 1/2 LSB Midscale FS + 1/2 LSB FS 9.9976 9.9964 5.0012 5.0000 0.0012 0.0000 9.99951 9.9927 0.0024 0.0000 9.9976 10.000
Output Code* DB11 (MSB) DB0 (LSB) 1111 1111 1111 1 1 1 1 1 1 1 1 1 1 1 1 1000 0000 000 1000 0000 0000 0000 0000 000 0000 0000 0000
*The symbol"" indicates a 0 or 1 with equal probability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADC912A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
4
REV. B
ADC912A WAFER TEST LIMITS (@ V
Parameter Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Analog Input Resistance Logic Input High Voltage Logic Input Low Voltage Logic Input Current Logic Output High Voltage Logic Output Low Voltage Positive Supply Current Negative Supply Current
DD
= +5 V, VSS = 12 V or 15 V, VREF = 5 V, AIN = 0 V to 10 V, and TA = 25 C, unless otherwise noted.)
Conditions ADC912AG Limit ±1 ±1 ±8 ±8 4/6 2.4 0.8 ±1 4 0.4 7 5 Unit LSB max LSB max LSB max LSB max k min/max V min V max µA max V min V max mA max mA max
Symbol INL DNL VZSE G FSE RA I N VINH VINL II N V OH V OL ID D ISS
Guaranteed by Design CS, RD, HBEN CS, RD, HBEN CS, RD, HBEN ISOURCE = 0.2 mA ISINK = 1.6 mA VDD = +5 V, CS = RD = VDD, AIN = +10 V VSS = 12 V, CS = RD = VDD, AIN = +10 V
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
10V C1 5V C1
R + C2 R + C2
1 2 3 4 5 6 24 23
R C1 R + C2 + C2
+5V
15V
C1 2 2 NC
21
R R
ADC912A
20
NC
7 8 9 10 11
TOP VIEW 1 9 (Not to Scale)
17
1 8 NC
R
1 6 NC 1 5 NC 1 4 NC 1 3 NC
R = 10 C1 = 0.01 F C2 = 4.7 F NC = NO CONNECT POWER SUPPLY SEQUENCE: +5V, 15V, 5V, +10V
12
Figure 9. Burn-In Circuit
REV. B
5
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