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Details, datasheet, quote on part number:ADCMP562
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Datasheet text preview:
Preliminary Technical Data
FEATURES
Differential PECL compatible outputs 1 ns propagation delay input to output 100 ps propagation delay dispersion Input common-mode range: 2.0 V to +3.0 V Input differential range Robust input protection Differential latch control Power supply rejection greater than 70 dB 700 ps minimum pulse width 1.5 GHz equivalent input rise time bandwidth Typical output rise/fall time of 500 ps Programmable hysteresis
Dual High Speed PECL Comparators ADCMP561/ADCMP562
FUNCTIONAL BLOCK DIAGRAM
NONINVERTING INPUT Q OUTPUT
INVERTING INPUT
ADCMP561/ ADCMP562
Q OUTPUT
04687-0-001
LATCH ENABLE INPUT
LATCH ENABLE INPUT
Figure 1.
GENERAL DESCRIPTION
The ADCMP561/ADCMP562 are high speed comparators fabricated on Analog Devices' proprietary XFCB process. The devices feature a 1 ns propagation delay with less than 150 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of high speed comparators. A separate programmable hysteresis pin is available on the ADCMP562. A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from -2.0 V to +3.0 V. Outputs are complementary digital signals that are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 to VDD - 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation. The ADCMP561/ADCMP562 are specified over the industrial temperature range (-40°C to +85°C). The ADCMP561 is available in a 16-lead QSOP package. The ADCMP562 is available in a 20-lead QSOP package.
APPLICATIONS
Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADCMP561/ADCMP562 TABLE OF CONTENTS
Specifications.... 3 Absolute Maximum Ratings... 5 Thermal Considerations..... 5 ESD Caution.......... 5 Pin Configuration and Function Descriptions..... 6 Timing Information ....... 8 Application Information......... 9 Clock Timing Recovery ...... 9
Preliminary Technical Data
Optimizing High Speed Performance .......9 Comparator Propagation Delay Dispersion ......9 Comparator Hysteresis ..... 10 Minimum Input Slew Rate Requirement ........ 10 Typical Application Circuits.......... 11 Typical Performance Characteristics .......... 12 Outline Dimensions ..... 14 Ordering Guide ........ 14
REVISION HISTORY
Revision PrA: Initial Version
Rev. PrA | Page 2 of 14
Preliminary Technical Data SPECIFICATIONS
ADCMP561/ADCMP562
ADCMP561/ADCMP562 Electrical Characteristics (VCC = +5.0 V, VEE = -5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted.) Table 1.
Parameter DC INPUT CHARACTERISTICS1 Input Common-Mode Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Open-Loop Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Voltage Range Latch Enable Differential Input Voltage Input High Current Input Low Current Latch Setup Time Latch to Output Delay Latch Minimum Pulse Width Latch Hold Time DC OUTPUT CHARACTERISTICS Output Voltage--High Level Output Voltage--Low Level Rise Time Fall Time AC PERFORMANCE Propagation Delay Propagation Delay Propagation Delay Tempco Prop Delay Skew--Rising Transition to Falling Transition Within Device Propagation Delay Skew-- Channel-to-Channel Propagation Delay Dispersion vs. Duty Cycle Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Slew Rate Propagation Delay Dispersion vs. Common-Mode Voltage Symbol VCM VOS DVOS/dT IBC -IN = 0 V, +IN = 0 V Conditions Min -2.0 -5 -10.0 Typ Max 3.0 +5 +10.0 Unit V V mV mV µV/°C µA nA/°C µA pF k k dB dB mV V V µA µA ps ps ps ps VDD - 0.81 VDD - 1.54 500 500 750 850 0.5 100 100 1 MHz, 1 ns tR, tF 50 mV to 1.5 V 20 mV to 100 mV 0 V to 1 V swing, 20% to 80%, 600 ps and 2 ns 1 V swing, -1.5VCM to +2.5VCM 50 100 100 100 100 V V ps ps ps ps ps/°C ps ps ps ps ps ps ps
@ -IN = -2 V, +IN = +3 V
-10.0 -3.0
CIN
CMRR
VCM = -2.0 V to +3.0 V
±3.0 ±3.0 10.0 ±5 0.5 ±1.0 1.75 100 600 60 70 ±0.5
+10.0 +3.0
VLCM VLD @ 0.0 V @ -2.0 V 250 mV overdrive 250 mV overdrive 250 mV overdrive 250 mV overdrive PECL 50 to VDD - 2.0 V PECL 50 to VDD - 2.0 V 10% to 90% 10% to 90% 1 V overdrive 20 mV overdrive
VDD - 2.0 0.4 -150 -150 500 750 750 500 VDD - 1.05 VDD - 1.95
VDD 2.0 +150 +150
tS tPLOH, tPLOL tPL tH VOH VOL tR tF tPD tPD
1
Under no circumstances should the input voltages exceed the supply voltages. Rev. PrA | Page 3 of 14
ADCMP561/ADCMP562
Parameter Equivalent Bandwidth Toggle Rate Minimum Pulse Width Unit-to-Unit Propagation Delay Skew POWER SUPPLY Positive Supply Current Negative Supply Current Logic Supply Current Logic Supply Current Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage Power Dissipation Power Dissipation Power Supply Sensitivity--VCC Power Supply Sensitivity--VEE Power Supply Sensitivity--VDD HYSTERESIS (ADCMP562 Only) Hysteresis Symbol BW Conditions 0 V to 1 V swing, 20% to 80%, 50 ps tr, tf >50% Output Swing tPD from 10 ns to 750 ps < ±25 ps
Preliminary Technical Data
Min Typ 1500 650 750 100 IVCC IVEE IVDD IVDD VCC VEE VDD @ +5.0 V @ -5.2 V @ 3.3 V without load @ 3.3 V with load Dual Dual Dual Dual, without load Dual, with load 3.2 22 9 60 5.0 -5.2 3.3 160 220 68 80 70 5 28 13 70 5.25 -5.45 5.0 190 250 Max Unit MHz MHz ps ps mA mA mA mA V V V mW mW dB dB dB mV
PW
4.75 -4.96 2.5
PSSVCC PSSVEE PSSVDD 0
40
Rev. PrA | Page 4 of 14
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2. ADCMP561/ADCMP562 Stress Ratings
Parameter Supply Voltages Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VDD to GND) Ground Voltage Differential Input Voltages Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -6.0 V to +0.5 V -0.5 V to +6.0 V -0.5 V to +0.5 V -3.0 V to +4.0 V -7.0 V to +7.0 V -0.5 V to +5.5 V 30 mA -40°C to +85°C 125°C -65°C to +150°C
ADCMP561/ADCMP562
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CONSIDERATIONS
The ADCMP562 QSOP 20-lead package option has a JA (junction-to-ambient thermal resistance) of TBD°C/W in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 14
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