|Category||Communication => Network => Switches => Switches/Multiplexers|
|Description||4/8 Channel Fault-protected Analog Multiplexers|
|Datasheet||Download ADG508FB datasheet
FEATURES Low On Resistance (300 Typ) Fast Switching Times 250 ns Max t OFF 250 ns Max Low Power Dissipation (3.3 mW Max) Fault and Overvoltage Protection +55 V) All Switches OFF with Power Supply OFF Analog Output of ON Channel Clamped within Power Supplies if an Overvoltage Occurs Latch-Up Proof Construction Break before Make Construction TTL and CMOS Compatible Inputs APPLICATIONS Existing Multiplexer Applications (Both Fault-Protected and Nonfault-Protected) New Designs Requiring Multiplexer Functions GENERAL DESCRIPTION
2. ON channel turns off while fault exists. 3. Low RON. 4. Fast Switching Times. 5. Break-Before-Make Switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. Trench Isolation Eliminates Latch-up. A dielectric trench separates the p and n-channel MOSFETs thereby preventing latch-up.
The ADG508F, ADG509F, and ADG528F are CMOS analog multiplexers, the ADG508F and ADG528F comprising eight single channels and the ADG509F comprising four differential channels. These multiplexers provide fault protection. Using a series n-channel, p-channel, n-channel MOSFET structure, both device and signal source protection is provided in the event of an overvoltage or power loss. The multiplexer can withstand continuous overvoltage inputs from +55 V. During fault conditions, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. This protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources that drive the multiplexer. The ADG508F and ADG528F switch one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1, and A2. The ADG509F switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines A0 and A1. The ADG528F has on-chip address and control latches that facilitate microprocessor interfacing. An EN input on each device is used to enable or disable the device. When disabled, all channels are switched OFF.
1. Fault Protection. The ADG508F/ADG509F/ADG528F can withstand continuous voltage inputs from +55 V. When a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows.
*N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); = 0.15" Small Outline IC (SOIC), = 0.3" Small Outline IC (SOIC).
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001Parameter ANALOG SWITCH Analog Signal Range RON
RON Drift RON Match LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage I D (OFF) ADG508F/ADG528F ADG509F Channel ON Leakage D, IS (ON) ADG508F/ADG528F ADG509F FAULT Output Leakage Current (With Overvoltage) Input Leakage Current (With Overvoltage) Input Leakage Current (With Power Supplies OFF) DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, VINL Input Current, IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 1 tTRANSITION tOPEN tON (EN, WR) tOFF (EN, RS) tSETT, Settling Time 0.01% ADG528F Only tW, Write Pulsewidth tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulsewidth Charge Injection OFF Isolation CS (OFF) CD (OFF) ADG508F/ADG528F ADG509F POWER REQUIREMENTS IDD ISS
NOTES 1 Guaranteed by design, not subject to production test. Specifications subject to change without notice.0 V, Test Circuit 10 V, Test Circuit VD = VEN 0 V Test Circuit 6
= 35 pF; 10 V; Test Circuit = 35 pF; 5 V; Test Circuit = 35 pF; 5 V; Test Circuit = 35 pF; 5 V; Test Circuit = 35 pF; 5 V0 , CL= 1 nF; Test Circuit = 15 pF, = 100 kHz; 7 V rms; Test Circuit 13
ON Switch Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff Time, tOFF (RS). Note: All digital input signals rise and fall times are measured from = 20 ns.
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