|Description||1 or 2 Phase Imvp-iii Compatible Core Controller For Latest Intel Mobile Processors|
|Datasheet||Download ADP3203 datasheet
FEATURES Pin Selectable or 2-Phase Operation Backward Compatible to IMVP-II Excellent Static and Dynamic Current Sharing Superior Load Transient Response with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectifier Control for Extended Battery Life Cycle-by-Cycle Current Limiting Hiccup or Latched Overload Protection Transient-Glitch-Free Power Good Soft Start Eliminates Power-On In-Rush Current Surge Two-Level Over-Voltage and Reverse-Voltage Protection APPLICATIONS IMVP II-III Core DC/DC Converters Fixed Voltage Mobile CPU Core DC/DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs ADP3203
HYSSET 1 DSHIFT 2 BSHIFT 3 HYSTERESIS SETTING & SHIFT-MUX VR
The or 2-phase hysteretic peak current DC-DC buck converter controller dedicated to power a mobile processor's core. The optimized low voltage design is powered from the 3.3 V system supply and draws only 10 µA maximum in shutdown. The nominal output voltage is set a 5-bit VID code. To accommodate the transition time required by the newest processors for on-the-fly VID changes, the ADP3203 features high-speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3203 features active voltage positioning with ADOPTTM optimal compensation to ensure a superior load transient response. The output signal interfaces with the ADP3415 MOSFET driver that is optimized for high speed and high efficiency for driving both the top and bottom MOSFETs of the buck converter. The ADP3203 is capable of controlling the synchronous rectifier to extend battery lifetime in light load conditions.ENABLE _UVLO MAIN BIAS PWRGD BLANKER
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= 25 °C, High (H) = VCC, Low (L) 0 V, VCC = H, VCOREFB = VDAC ( VDACOUT), VREG = VCS = VVID 1.25 V, ROUT 100 k, COUT = 10 pF, CSS = 47 nF, RPWRGD 1.2 V, RCLAMP k to VCC, HYSSET, BSHIFT, DSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a negative sign. Negative sign is disregarded for min and max values. Parameter Symbol Conditions Min Typ Max Units
SUPPLY-UVLO-SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold VCCH VCCL UVLO Hysteresis Shutdown Threshold (CMOS Input) POWERGOOD-CORE FEEDBACK Core Feedback Threshold Voltage VCCHYS VSDTH VCOREFBH ICC ICCUVLO ICCSD
V < VDAC 1.675 V VCOREFB ramping up VCOREFB ramping down VCOREFB ramping up VCOREFB ramping down VCOREFB = VDACOUT VCOREFB = 0.8 VDACOUT VCC 3.3 VPower Good Output Voltage (open drain output)
VRAMP = VCOREFB 1.27 V VSS ramping down VSS ramping up VRAMP = VCOREFB 1.27 V VSS ramping up
VID DAC VID Input Threshold (CMOS Inputs) VID Input Current (Internal Active Pull-up) Output Voltage Accuracy Settling Time2See VID Code Table 1 VDAC VDAC/VDAC V < VDAC V < VDAC V tDACS3 VDAC 0.5 V, CDAC 10 nF
Notes: 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by characterization. 3 Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value. 4 40 mVPP amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point 50% of the output voltage swing. 5 Measured between the 30% and 70% points of the output voltage swing. 6 Two test conditions: is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (VCOREFB,BAD V at VVID 1.25 V setting) to the COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay time. 2) PWRGD is forced to fail (VCOREFB,BAD V at VVID 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time. 7 Guaranteed by design.
Parameter CORE COMPARATOR Input Offset Voltage (Ramp-Reg) Input Bias Current Output Voltage (OUT1,OUT2) Propagation Delay Time2 Rise and Fall Time2 Noise Blanking Time2 CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias CurrentSymbol VCOREOS IREG, IRAMP VOUT_H VOUT_L tOUT_R5 tOUT_F5 tBLNK
Conditions VREG 1.25 V VREG = VRAMP 1.25 V VCC 3.0 V VCC TA = Full Range OUT L-H Transition OUT H-L Transition
TA = Full Range CURRENT SENSE MULTIPLEXER Trans-Resistance Common Mode Voltage Range7 HYSTERESIS SETTING Hysteresis Current = VCS2 IRAMP_H, -ICSP_H Switch is ON Switch is OFF 0 VREG 1.25 V VRAMP = 1.23 V,BOM=H IHYSSET 10 µA IHYSSET 100 µA VRAMP 1.27 V, BOM = H IHYSSET 10 µ IHYSSET 100 µ VRAMP 1.23 V, BOM = L IHYSSET 10 µ IHYSSET 100 µ VRAMP 1.27 V, BOM = L IHYSSET 10 µ IHYSSET 100 µHysteresis Reference Voltage CURRENT LIMIT SETTING Hysteresis Current
VHYSSET ICS VRAMP 1.23 V VREG = VCS = VCOREFB 1.25 V IHYSSET 10 µ
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