|Description||Multi-phase Imvp-iii Compliant Core Controller For Mobile Intel Cpus|
|Datasheet||Download ADP3204 datasheet
FEATURES Pin Selectable or 3-Phase Operation Excellent Current Sharing Characteristics Backward Compatible to IMVP-II Superior Load Transient Response with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectifier Control Extends Battery Life Smooth Output Transition During VID Code Change Cycle-by-Cycle Current Limiting Hiccup or Latched Overload Protection Transient-Glitch-Free Power Good Soft Start Eliminates Power-On In-Rush Current Surge Two-Level Over-Voltage and Reverse-Voltage Protection APPLICATIONS IMVP-II and IMVP-III Core DC/DC Converters Fixed Voltage Mobile CPU Core DC/DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies3-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs ADP3204
HYSSET DSHIFT BSHIFT DPRSHIFT BOM DSLP DPRSLP HYSTERESIS SETTING & SHIFT-MUX VR OUT3 PHASE SPLITTER OUT2 OUT1
The or 3-phase hysteretic peak current DC-DC buck converter controller dedicated to power a mobile processor's core. The optimized low voltage design is powered from the 3.3 V system supply. The nominal output voltage is set a 5-bit VID code. To accommodate the transition time required by the newest processors for on-the-fly VID changes, the ADP3204 features high-speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3204 features active voltage positioning with ADOPTTM optimal compensation to ensure a superior load transient response. The output signals interface with a maximum of three ADP3415 MOSFET drivers that are optimized for high speed and high efficiency for driving both the top and bottom MOSFETs of the buck converter. The ADP3204 is capable of controlling the synchronous rectifiers to extend battery lifetime in light load conditions.BOM DPSLP DPRSLP VID TRANSIENT DETECTOR & SHIFT SELECTOR
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Parameter SUPPLY-UVLO-SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold VCCH VCCL UVLO Hysteresis ShutdownThreshold (CMOS Input) POWERGOOD Core Feedback Threshold Voltage VCCHYS VSDTH VCOREFBH Symbol ICC ICCUVLO ICCSD Conditions
(TA =25°C, High (H) = VCC, Low (L) 0 V, VCC = H, VCOREFB = VDAC DACOUT REG CS = VVID 1.25 V, CDACRAMP = 100 pF, OUT3 SS PWRGD CLAMP k to VCC, HYSSET, BSHIFT, DSHIFT, and DPRSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a negative sign. Negative sign is disregarded for min and max values.
Min Typ 3.0 V VCC = H VCC ramping up, VSS= 0 V VCC ramping down, VSS floating Max 425 10 Units mA µA
V < VDAC 1.675 V VCOREFB ramping up VCOREFB ramping down VCOREFB ramping up VCOREFB ramping down VCOREFB =VDACOUT VCOREFB = 0.8 VDACOUTPower Good Output Voltage (open drain output)
SOFT-START/HICCUPTIMER Charge/Discharge Current Soft-Start Enable/Hiccup TerminationThreshold
Soft-Start Termination/Hiccup EnableThreshold VIDDAC VID Input Threshold (CMOS Inputs) VID Input Current (Internal Active Pull-up) Output Voltage Accuracy Settling Time2 DACRAMP Inner Resistance7
VSS 0 V VSS 0.5 V VREG 1.25 V, VRAMP = VCOREFB 1.27 V VSS ramping down VSS ramping up8 VRAMP = VCOREFB 1.27 V VSS ramping upVID = L See VID Code Table V < VDAC V < VDAC 0.600 V CDACRAMP 100 pF CDACRAMP 1 nF
Notes: 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by characterization. 3 Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value. 4 40 mVPP amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point 50% of the output voltage swing. 5 Measured between the 30% and 70% points of the output voltage swing. 6 Two test conditions: is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (VCOREFB,BAD V at VVID 1.25 V setting) to the COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay time. 2) PWRGD is forced to fail (VCOREFB,BAD V at VVID 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time. 7 Measured between DACRAMP and DACOUT pins. 7 Guaranteed by design.
Parameter CORE COMPARATOR Input Offset Voltage (Ramp-Reg) Input Bias Current OutputVoltage (OUT1, OUT2, and OUT3) Propagation Delay Time2 Rise and Fall (OUT1, OUT2, and OUT3) Noise Blanking Time2 Symbol VCOREOS IREG, IRAMP VOUT_H VOUT_L tOUT_R5 tOUT_F5 tBLNK Conditions VREG 1.25 V VREG = VRAMP 1.25 V VCC 3.0 V VCC TA = Full Range OUT L-H transition OUT H-L transition VCS- 1.25 V VCS+ 1.25 VCURRENT LIMIT COMPARATOR Input Offset Voltage VCLIMOS Input Bias Current ICS+
TA = Full Range CURRENT SENSE MULTIPLEXER Trans-Resistance
Common Mode Voltage Range HYSTERESIS SETTING Hysteresis Current IRAMP_H, -ICSP_H
Hysteresis Reference Voltage CURRENT LIMIT SETTING Hysteresis Current
VHYSSET ICS VRAMP 1.23 V VREG = VCS = VCOREFB 1.25 V IHYSSET 10 µ
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