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Part: ADP3204JCP-Reel
Category:
Description: Multi-phase Imvp-iii Compliant Core Controller For Mobile Intel Cpus
Company: Analog Devices
Datasheet: Download ADP3204JCP-Reel datasheet File size : 841 kB
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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Pin Selectable 1, 2, or 3-Phase Operation Excellent Current Sharing Characteristics Backward Compatible to IMVP-II Superior Load Transient Response with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectifier Control Extends Battery Life Smooth Output Transition During VID Code Change Cycle-by-Cycle Current Limiting Hiccup or Latched Overload Protection Transient-Glitch-Free Power Good Soft Start Eliminates Power-On In-Rush Current Surge Two-Level Over-Voltage and Reverse-Voltage Protection APPLICATIONS IMVP-II and IMVP-III Core DC/DC Converters Fixed Voltage Mobile CPU Core DC/DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies
3-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs ADP3204
FUNCTIONAL BLOCK DIAGRAM
VCC
ADP3204
HYSSET DSHIFT BSHIFT DPRSHIFT BOM DSLP DPRSLP HYSTERESIS SETTING & SHIFT-MUX VR OUT3 PHASE SPLITTER OUT2 OUT1
CLIM
CS3 CS2 CURRENT SENSE MUX CS1 CS+ CSRAMP
EN
CORE
VID4 VID3 VID2 VID1 VID0
REG
DPRSLP VID GEN
BOM
VID MUX & REG
5-BIT VID DAC & FIXED REF
DSLP
DACOUT DACRAMP
DPRSLP
GENERAL DESCRIPTION
VR
The ADP3204 is a 1, 2, or 3-phase hysteretic peak current DC-DC buck converter controller dedicated to power a mobile processor's core. The optimized low voltage design is powered from the 3.3 V system supply. The nominal output voltage is set by a 5-bit VID code. To accommodate the transition time required by the newest processors for on-the-fly VID changes, the ADP3204 features high-speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3204 features active voltage positioning with ADOPTTM optimal compensation to ensure a superior load transient response. The output signals interface with a maximum of three ADP3415 MOSFET drivers that are optimized for high speed and high efficiency for driving both the top and bottom MOSFETs of the buck converter. The ADP3204 is capable of controlling the synchronous rectifiers to extend battery lifetime in light load conditions.
BOM DPSLP DPRSLP VID TRANSIENT DETECTOR & SHIFT SELECTOR
COREGD MONITOR SS-HICCUP TIMER & OCP SR CONTROL
COREFB SS DRVLSD CLAMP
PWRGD SD
PWRGD BLANKER ENABLE-UVLO-MAIN BIAS PM MODULE OVP & RVP
GND
REV. PrF
1/02
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel:781/329-4700 World Wide Web Site: http://www.analog.com Fax:781/326-8703 ©ANALOG DEVICES, INC., 2002
A0D, 32= C4=SCPECIpF, IC=A47 InF, RNS1= (680V to), 1.2 V,= RV P0 FC T O V 10 k C =10
Parameter SUPPLY-UVLO-SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold VCCH VCCL UVLO Hysteresis ShutdownThreshold (CMOS Input) POWERGOOD Core Feedback Threshold Voltage VCCHYS VSDTH VCOREFBH Symbol IC C ICCUVLO I CCSD Conditions
PRELIMINARY TECHNICAL DATA
(TA =25°C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB = VDAC DACOUT REG CS = VVID = 1.25 V, CDACRAMP = 100 pF, ROUT1 =ROUT2 = ROUT3 = OUT1 OUT2 OUT3 SS PWRGD CLAMP = 5.1 k to VCC, HYSSET, BSHIFT, DSHIFT, and DPRSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a negative sign. Negative sign is disregarded for min and max values.
Min Typ 7 SD = L, 3.0 V VCC 3.6 V SD = H VCC ramping up, VSS= 0 V VCC ramping down, VSS floating Max 15 425 10 Units mA µA µA V V m V V
2.9 2.65 50 VCC/2
0.9 V < VDAC < 1.675 V VCOREFB ramping up VCOREFB ramping down VCOREFB ramping up VCOREFB ramping down VCOREFB =VDACOUT VCOREFB = 0.8 VDACOUT
1.12 VDAC 1.14 VDAC 1.10VDAC 1.12 VDAC 0.88VDAC 0.90 VDAC 0.86VDAC 0.88 VDAC 0.95 VCC 0
100
V V V V VCC 0.8 V V
µs µA µA
Power Good Output Voltage (open drain output)
Masking Time
2
VPWRGD tPWRGDMSK6 ISS VSSEN
SOFT-START/HICCUPTIMER Charge/Discharge Current Soft-Start Enable/Hiccup TerminationThreshold
Soft-Start Termination/Hiccup EnableThreshold VIDDAC VID Input Threshold (CMOS Inputs) VID Input Current (Internal Active Pull-up) Output Voltage Accuracy Settling Time2 DACRAMP Inner Resistance7
VSSTERM
VSS = 0 V VSS = 0.5 V VREG = 1.25 V, VRAMP = VCOREFB = 1.27 V VSS ramping down VSS ramping up8 VRAMP = VCOREFB = 1.27 V VSS ramping up
55 15
80 150 1.75 2.00 VCC/2 90 0.600 1.0 8.5 3.5 35 10
200
m V m V V V µA
2.25
VVID0..4 IVID0..4 VDAC VDAC/VDAC tDACS3 RDACRAMP
VID 0..4 = L See VID Code Table 1 0.750 V < VDAC < 0.850 V 0.825 V < VDAC < 0.600 V CDACRAMP = 100 pF CDACRAMP = 1 nF
1.750 +1.0 +8.5
V % m V µs µs k
Notes: 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by characterization. 3 Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value. 4 40 mVPP amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing. 5 Measured between the 30% and 70% points of the output voltage swing. 6 Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay time. 2) PWRGD is forced to fail (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time. 7 Measured between DACRAMP and DACOUT pins. 7 Guaranteed by design.
2
REV. PrF
PRELIMINARY TECHNICAL DATA ADP3204
Parameter CORE COMPARATOR Input Offset Voltage (Ramp-Reg) Input Bias Current OutputVoltage (OUT1, OUT2, and OUT3) Propagation Delay Time2 Rise and Fall Time2 (OUT1, OUT2, and OUT3) Noise Blanking Time2 Symbol VCOREOS IREG, IRAMP VOUT_H VOUT_L tRMPOUT_PD4 tOUT_R5 t O U T _ F5 tBLNK Conditions VREG = 1.25 V VREG = VRAMP = 1.25 V VCC = 3.0 V VCC = 3.6 V TA = 25°C TA = Full Range OUT L-H transition OUT H-L transition VCS- = 1.25 V VCS+ = 1.25 V
TA = 25° C
Min
Typ ±1.5 ±1
Max
Unit m V µA V V ns ns ns ns ns ns m V
µA ns ns
2.5 0
3.0 0.8 30 40 10 10
7 7 80 120 ±4
5 30 50
CURRENT LIMIT COMPARATOR Input Offset Voltage VCLIMOS Input Bias Current ICS+
Propagation Delay Time2 tCLPD
4
±6 3
60 100
TA = Full Range CURRENT SENSE MULTIPLEXER Trans-Resistance
R CS1-CS+ , R CS2-CS+ , RCS3-CS+
Switch is ON Switch is OFF VCS1 = VCS2, = VCS3 0
150 10 2
M V
Common Mode Voltage Range HYSTERESIS SETTING Hysteresis Current IRAMP_H, -ICSP_H
VREG = 1.25 V VRAMP = 1.23 V, BOM = H IHYSSET = 10 µA IHYSSET = 100 µA VRAMP = 1.27 V, BOM = H IHYSSET = 10 µ IHYSSET = 100 µ VRAMP = 1.23 V, BOM = L IHYSSET = 10 µ IHYSSET = 100 µ VRAMP = 1.27 V, BOM = L IHYSSET = 10 µ IHYSSET = 100 µ
8 80 8 80 6.4 64 6.4 64 1.53
10 100 10 100 8 80 8 80 1.7
12 120 12 120 9.6 96 9.6 96 1.87
µA µA µ µ µ µ µ µA V
Hysteresis Reference Voltage CURRENT LIMIT SETTING Hysteresis Current
VHYSSET ICS VRAMP = 1.23 V VREG = VCS = VCOREFB = 1.25 V IHYSSET = 10 µ
VCS+ = 1.23 V BOM = H
27 268 18 178 21 212 14 140
31.5
36
µA µA µA µA µA µA µA µA
IHYSSET = 100 µ
VCS+ = 1.27 V, BOM = H
301.5 335 21.5 25
IHYSSET = 10 µ IHYSSET = 100 µ
VCS+ = 1.23 V, BOM = L
201.5 225 25.5 30
IHYSSET = 10 µ
IHYSSET = 100 µ
VCS+ = 1.27 V, BOM = L
241.5 271 17.5 161.5 21 183
IHYSSET = 10 µ IHYSSET = 100 µ
REV. PrF
3
PRELIMINARY TECHNICAL DATA
ADP3204SPECIFICATIONS1
Parameter SHIFT SETTING Battery-Shift Current Symbol IRAMPB, ICS+B VBSHIFT I R A M P D, I C S + D VVID = 1.25 V RDSHIFT = 12.5 k, BOM = H DSLP = L 90 Conditions VVID = 1.25 V RBSHIFT = 12.5 k, BOM = L DSLP = H Min 90 Typ 100 Max 110 Units µA V 110 µA
Battery-Shift Reference Voltage DeepSleep-Shift Current
VDAC 100
DeepSleep-Shift Reference Voltage DeeperSleep-Shift Current
VDSHIFT IREGDPR , -ICOREFBDPR VDRPSHIFT
VVID = 1.25 V, IDPRSHIFT = 100 µA, DPRSLP = H
-90
VDAC -100
-110
V µA
DeeperSleep-Shift Reference Voltage SHIFT CONTROL INPUTS BOM Threshold (CMOS Input) DSLP Threshold CMOS Input) DPRSLP Mode Threshold (CMOS Input)
LOW-SIDE DRIVE CONTROL Output Voltage (CMOS Output) Output Current
VDAC
V
VBOM VDSLP VDPRSLP
VCC/2 VCC/2 VCC/2
V V V
VD R V L S D I DRVLSD
DPRSLP = H DPRSLP = L DPRSLP = L, VDRVLSD = 1.5 V DPRSLP = H
0 0 . 7 VC C 0.5 0.5
0.4 VCC
V V mA mA
OVER/REVERSE VOLTAGE PROTECTION-CORE FEEDBACK Over-Voltage Threshold
VCOREFB,OVP
VCOREFB rising VCOREFB falling VCOREFB falling VCOREFB rising 0.7 VCC VCLAMP = 1.5 V, VVID = 1.25 V VCOREFB = VDAC VCOREFB = 2.2 V
2.0 1.95 0.3 0.1 VCC 10 1 4
V V V V V µA mA
Reverse-Voltage Threshold Output Voltage (open drain output) Output Current
VCOREFB,RVP VCLAMP ICLAMP
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Model ADP3204JCP-Reel ADP3204JCP-Reel7
Temperature Range 0°C to 100°C 0°C to 100°C
Package Description LFCSP-32 LFCSP-32
Package Option CP-32 CP-32
Input Supply Voltage (VCC) ..... -0.3 V to +7 V UVLO Input Voltage ...... -0.3 V to +7 V All Other Inputs/Outputs ............ VCC + 0.3 V OperatingAmbientTemperatureRange ..... 0°C to +100°C JunctionTemperatureRange .... 0°C to +150°C JA ......... 98°C/W Storage Temperature Range .... -65°C to 150°C Lead Temperature (Soldering, 10 sec.) .......... +300°C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
4
REV. REV. PrF
PRELIMINARY TECHNICAL DATA ADP3204
TABLE1.VIDCODE
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOUT 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 1.250 1.200 1.150 1.100 1.050 1.00 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 0.750 0.725 0.700 0.675 0.650 0.625 0.600
REV. PrF
5
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