Details, datasheet, quote on part number: ADP3205
PartADP3205
Category
DescriptionMulti-phase Imvp-iv Core Controller For Mobile Cpus
CompanyAnalog Devices
DatasheetDownload ADP3205 datasheet
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Features, Applications
Multiphase IMVP-IV Core Controller for Mobile CPUs ADP3205

FEATURES Pin Programmable or 3-Phase Operation Excellent Static and Dynamic Current Sharing Superior Load Transient Response when Used with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectification Control for Optimized Light Load Efficiency Soft DAC Output Voltage Transition for VID Change Cycle-by-Cycle Current Limiting Latched or Hiccup Current Overload Protection Masked Power Good during Output Voltage Transients Soft Start-Up without Power-On In-Rush Current Surge 2-Level Overvoltage and Reverse-Voltage Protection APPLICATIONS IMVP-IV CPU Core DC-to-DC Converters Programmable Output Power Supplies GENERAL DESCRIPTION

The or 3-phase hysteretic peak current mode dc-to-dc buck converter controller dedicated to powering a mobile processor's core. The chip optimized low voltage design runs from the 3.3 V system supply. The chip contains a precision 6-bit DAC whose nominal output voltage is set by VID code. The ADP3205 features high speed operation to allow a minimized inductor size that results in the fastest possible change of current to the output. To further minimize the number of output capacitors, the converter features active voltage positioning enhanced with ADOPT optimal compensation to ensure a superior load transient response. The output signals interface with ADP3415 MOSFET drivers, which that are optimized for high speed and high efficiency. The ADP3205 is capable of providing synchronous rectification control to extend battery lifetime in light load conditions. The ADP3205 is specified over the extended commercial temperature range to 100C and is available a 40-lead LFCSP package.

TSYNC 40 PSI HYSSET CLIM/ZCS CMP HYS/CLIM CONTROL AND CS MUX/ PHASE CONTROL VDACREF CURRENT SENSE HYSTERESIS SET MUX AND VBG CLIM SET

DRVCTRL DPSLP VREF BOOTSET DPRSET DPRSLP VID1 VID0 PWRGD CLKEN TPWRGD DPWRGD BOOT SS 19 SS/LATCH-OFF TIMER PRWGD DELAY VREF VBG PRWGD MASKING COREGD EOFSS ALARM LATCHEN CORE BELOW CMP DAC RES NETWORK CORE ABOVE CMP DACREFFB VREF VBG BOOT REF MUX DACREF DPSHIFT SET DPSHIFT

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 2003 Analog Devices, Inc. All rights reserved.

< 100C, High (H) = VCC, Low (L) 0 V, VCC = H, VCOREFB = VREFFB = VDAC ( VDACREF), VREG = VCS = VVID 1.25 V, RDACREFFB 50 , DACREFFB = 10 pF, CSS 0.047 F, RPWRGD k to VCC, RCLAMP k to VCC, HYSSET, DPSHIFT is open, DPSLP = H, DPRSLP = L, VBOOTSET 1.0 V, VDPRSET 1.0 V, unless otherwise noted.) Current sunk by a pin has a positive sign; current sourced by a pin has a negative sign.

Parameter SUPPLY UVLO SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold Symbol ICC ICC(UVLO) ICCSD VCCH VCCL UVLO Hysteresis2 Shutdown Threshold (SD CMOS Input) CORE FEEDBACK POWER GOOD Core Feedback Threshold Voltage VCCHYS VSDTH Conditions Min Typ 3.0 V VCC = H VCC Ramping Up, VSS 0 V VCC Ramping Down VSS Floating VCC/2 Max 11 450 Unit mV V

Power Good Output Voltage (Open-Drain Output) Masking Time CLOCK ENABLER Output Voltage Delay Time (PWRGD to CLKEN) DELAYED POWER GOOD Output Current (Open-Drain Output) POWER GOOD DELAY TIMER Timing Threshold Input Current Input Resistance SOFT START/LATCH-OFF TIMER Charge Current Discharge Current Soft-Start Enable Threshold

VPWRGD tPWRGD, MSK3 VCLKENH VCLKENL tDCLKEN IDPWRGDH IDPWRGDL VTPWRGDTH ITPWRGD RTPWRGD ISS VSSEN

V < VDAC 1.708 V VCOREFB Ramping Up VCOREFB Ramping Down VCOREFB Ramping Up VCOREFB Ramping Down VCOREFB = VDAC VCOREFB = 0.8 VDAC VCC 3.3 V VCC 3.0 V, ICLKEN 10 A VCC 3.6 V, ICLKEN +10 A

VTPWRGD 3 V VTPWRGD 1.3 V VSS 0.5 V VSS 0.5 V VREG 1.25 V, VRAMP = VCOREFB 1.27 V VSS Ramping Down VSS Ramping Up2 VRAMP = VCOREFB 1.27 V VSS Ramping 10 A IVREF 10 A

Soft-Start Termination Threshold FIXED REFERENCE Output Voltage

VID PROGRAMMED DAC REFERENCE VID Input Threshold (MOS Inputs) VVID0..5 Output Voltage VDAC Static Tolerance (at a Given VID) VDAC/VDAC Settling Time tDACS4

Parameter DAC REFERENCE FEEDBACK Input Resistance CORE COMPARATOR Input Offset Voltage (RampReg) Input Bias Current Output Voltage (DRV1, DRV2, and DRV3) Propagation Delay Time RAMPDRV2, RAMPDRV3) Rise and Fall Time (DRV1, DRV2, and DRV3) Noise Blanking Time CURRENT SENSE MULTIPLEXER Trans-Resistance Symbol RDACREFFB VCOREOS IREG, IRAMP VDRV_H VDRV_L tDRV_R6 tDRV_F6 tBLNK VREG 1.25 V VREG = VRAMP 1.25 V VCC 3.0 V VCC = 25C Conditions Min Typ Max Unit A ns

DRV L-H Transition DRV H-L Transition MUX Switch Is ON MUX Switch Is OFF = VCS3 VCS 1.25 V VCS+ = 25C

Common-Mode Voltage Range CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Propagation Delay Time HYSTERESIS SETTING Hysteresis Current

VREG 1.25 V VCOREFB = VRAMP 1.23 V IHYSSET 100 A IHYSSET 10 A VRAMP 1.27 V IHYSSET 100 A IHYSSET 10 A

Hysteresis Reference Voltage CURRENT LIMIT SETTING Limit Setting Current

VHYSSET ICS VRAMP 1.23 V VREG = VCS = VCOREFB 1.25 V VCS+ 1.23 V IHYSSET 100 A IHYSSET 10 A VCS+ 1.27 V IHYSSET 100 A IHYSSET 10 A

DEEP SLEEP SHIFT SETTING AND CONTROL DPSHIFT Inner Resistance DPSLP Control Threshold (CMOS Input) DEEPER SLEEP VOLTAGE SETTING AND CONTROL7 Input Current DPRSET Gain (DPRSETDACREF) DPRSLP Control Threshold (CMOS Input)


 

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