SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter Single-Cycle Instruction Execution & Multifunction Instructions On-Chip Program Memory RAM or ROM & Data Memory RAM Integrated I/O Peripherals: Serial Ports, Timer, Host Interface Port (ADSP-2111 Only) FEATURES 25 MIPS, 40 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.g., EPROM ) Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel Operation ADSP-2111 Host Interface Port Provides Easy Interface 80C51, ADSP-21xx, Etc. Automatic Booting of ADSP-2111 Program Memory Through Host Interface Port Three Edge- or Level-Sensitive Interrupts Low Power IDLE Instruction PGA, PLCC, PQFP, and TQFP Packages MIL-STD-883B Versions Available GENERAL DESCRIPTION
MEMORY PROGRAM SEQUENCER PROGRAM MEMORY DATA MEMORY FLAGS (ADSP-2111) EXTERNAL ADDRESS BUS
This data sheet describes the following ADSP-2100 Family processors: 3.3 V Version of ADSP-2101 Low Cost DSP with Host Interface Port Custom ROM-programmed DSPs
The following ADSP-2100 Family processors are not included in this data sheet: ADSP-2100A ADSP-2165/66 DSP Microprocessor ROM-programmed ADSP-216x processors with powerdown and larger on-chip memories (12K Program Memory ROM, 1K Program Memory RAM, 4K Data Memory RAM) Mixed-Signal DSP Processors with integrated on-chip A/D and D/A plus powerdown Speed and feature enhanced ADSP-2100 Family processor with host interface port, powerdown, and instruction set extensions for bit manipulation, multiplication, biased rounding, and global interrupt masking ADSP-21xx processor with ADSP-2171 features plus 80K bytes of on-chip RAM configured as 16K words of program memory and 16K words of data memory.
ADSP-21msp5x The ADSP-2100 Family processors are single-chip microcomputers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-21xx processors are all built upon a common core. Each processor combines the core DSP architecture--computation units, data address generators, and program sequencer--with differentiating features such as on-chip program and data memory RAM, a programmable timer, one or two serial ports, and, on the ADSP-2111, a host interface port.
Refer to the individual data sheet of each of these processors for further information. REV. B
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Fabricated in a high speed, submicron, double-layer metal CMOS process, the highest-performance ADSP-21xx processors operate at 25 MHz with 40 ns instruction cycle time. Every instruction can execute in a single cycle. Fabrication in CMOS results in low power dissipation. The ADSP-2100 Family's flexible architecture and comprehensive instruction set support a high degree of parallelism. In one cycle the ADSP-21xx can perform all of the following operations:
Receive and transmit data via one or two serial ports Receive and/or transmit data via the host interface port (ADSP-2111 only)
Generate the next program address Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computation
The ADSP-2101, ADSP-2105, and ADSP-2115 comprise the basic set of processors of the family. Each of these three devices contains program and data memory RAM, an interval timer, and one or two serial ports. The a 3.3 volt power supply version of the it is identical to the ADSP-2101 in all other characteristics. Table I shows the features of each ADSP-21xx processor. The ADSP-2111 adds a 16-bit host interface port (HIP) to the basic set of ADSP-21xx integrated features. The host port provides a simple interface to host microprocessors or microcontrollers such as the 68000, or ISA bus.
TABLE OF CONTENTS GENERAL DESCRIPTION. 1 Development Tools. 4 Additional Information. 4 ARCHITECTURE OVERVIEW. 4 Serial Ports. 5 Host Interface Port (ADSP-2111). 6 Interrupts. 6 Pin Definitions. 7 SYSTEM INTERFACE. 7 Clock Signals. 7 Reset. 8 Program Memory Interface. 10 Program Memory Maps. 10 Data Memory Interface. 12 Data Memory Map. 12 Boot Memory Interface. 12 Bus Interface. 12 Low Power IDLE Instruction. 13 ADSP-216x Prototyping. 13 Ordering Procedure for ADSP-216x ROM Processors. 13 Wafer Products. 14 Functional Differences for Older Revision Devices. 14 Instruction Set. 15 SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163). 17 Recommended Operating Conditions. 17 Electrical Characteristics. 17 Supply Current & Power (ADSP-2101/2161/2163). 18 Power Dissipation Example. 19 Environmental Conditions. 19 Capacitive Loading. 19 Test Conditions. 20 SPECIFICATIONS (ADSP-2111). 21 Recommended Operating Conditions. 21 Electrical Characteristics. 21 Supply Current & Power. 22 Power Dissipation Example. 23 Environmental Conditions. 23
Capacitive Loading. 23 Test Conditions. 24 SPECIFICATIONS (ADSP-2103/2162/2164). 25 Recommended Operating Conditions. 25 Electrical Characteristics. 25 Supply Current & Power. 26 Power Dissipation Example. 27 Environmental Conditions. 27 Capacitive Loading. 27 Test Conditions. 28 TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163). 29 Clock Signals. 30 Interrupts & Flags. 31 Bus RequestBus Grant. 32 Memory Read. 33 Memory Write. 34 Serial Ports. 35 Host Interface Port (ADSP-2111). 36 TIMING PARAMETERS (ADSP-2103/2162/2164). 44 Clock Signals. 45 Interrupts & Flags. 46 Bus RequestBus Grant. 47 Memory Read. 48 Memory Write. 49 Serial Ports. 50 PIN CONFIGURATIONS 68-Pin PGA 51 68-Lead PLCC 52 80-Lead PQFP 53 80-Lead TQFP 53 100-Pin PGA 54 100-Lead PQFP (ADSP-2111). 55 PACKAGE OUTLINE DIMENSIONS 68-Pin PGA. 56 68-Lead PLCC. 57 80-Lead PQFP, 80-Lead TQFP. 58 100-Pin PGA. 59 100-Lead PQFP. 60 ORDERING GUIDE. 61-62
Feature Data Memory (RAM) Program Memory (RAM) Timer Serial Port 0 (Multichannel) Serial Port 1 Host Interface Port Speed Grades (Instruction Cycle Time) 10.24 MHz (76.9 ns) 13.0 MHz (76.9 ns) 13.824 MHz (72.3 ns) 16.67 MHz (60 ns) 20.0 MHz (50 ns) 25 MHz (40 ns) Supply Voltage Packages 68-Pin PGA 68-Lead PLCC 80-Lead PQFP 80-Lead TQFP 100-Pin PGA 100-Lead PQFP Temperature Grades K Commercial +70°C B Industrial +85°C T Extended to +125°C
Feature Data Memory (RAM) Program Memory (ROM) Program Memory (RAM) Timer Serial Port 0 (Multichannel) Serial Port 1 Supply Voltage Speed Grades (Instruction Cycle Time) 10.24 MHz (97.6 ns) 16.67 MHz (60 ns) 25 MHz (40 ns) Packages 68-Lead PLCC 80-Lead PQFP Temperature Grades K Commercial +70°C B Industrial to +85°C