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Details, datasheet, quote on part number:JM13903BIA
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Datasheet text preview:
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FEATURES Pretrimmed to 1.0% (AD532K) No External Components Required Guaranteed 1.0% max 4-Quadrant Error (AD532K) Diff Inputs for (X 1 X 2) (Y 1 Y2 )/10 V Transfer Function Monolithic Construction, Low Cost APPLICATIONS Multiplication, Division, Squaring, Square Rooting Algebraic Computation Power Measurements Instrumentation Applications Available in Chip Form
+VS
Internally Trimmed Integrated Circuit Multiplier AD532
PIN CONFIGURATIONS
Y2 Y1 VOS Z1 OUT 2
14 +VS 13 Y1
AD532
TOP VIEW (Not to Scale)
GND
VS 3 NC 4
AD532
12 Y2
Z
X2
TOP VIEW 11 VOS (Not to Scale) 10 NC 5 GND NC 6
9 8
X2 NC
OUT VS
X1
X1 7
NC = NO CONNECT OUT +VS NC
1
3
Z
2
20 19
Y1
18 Y2 17 NC 16 VOS 15 NC 14 GND
VS 4 NC 5 NC 6 NC 7 NC 8
9 10 11 12 13
AD532
TOP VIEW (Not to Scale)
PRODUCT DESCRIPTION
The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of ± 1.0% and a ± 10 V output voltage without the need for any external trimming resistors or output op amp. Because the AD532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. Further, the AD532 can be used as a direct replacement for other IC multipliers that require external trim networks (such as the AD530).
FLEXIBILITY OF OPERATION
NC
NC
NC
X1
NC = NO CONNECT
GUARANTEED PERFORMANCE OVER TEMPERATURE
The AD532 multiplies in four quadrants with a transfer function of (X1 X 2)(Y 1 Y 2)/10 V, divides in two quadrants with a 10 V Z/(X1 X2) transfer function, and square roots in one quadrant with a transfer function of ± 10 V Z. In addition to these basic functions, the differential X and Y inputs provide significant operating flexibility both for algebraic computation and transducer instrumentation applications. Transfer functions, such as XY/10 V, (X2 Y2)/10 V, ± X2/10 V and 10 V Z/(X1 X2), are easily attained and are extremely useful in many modulation and function generation applications, as well as in trigonometric calculations for airborne navigation and guidance applications, where the monolithic construction and small size of the AD532 offer considerable system advantages. In addition, the high CMRR (75 dB) of the differential inputs makes the AD532 especially well qualified for instrumentation applications, as it can provide an output signal that is the product of two transducergenerated input signals.
The AD532J and AD532K are specified for maximum multiplying errors of ± 2% and ± 1% of full scale, respectively at +25°C, and are rated for operation from 0°C to +70°C. The AD532S has a maximum multiplying error of ± 1% of full scale at +25°C; it is also 100% tested to guarantee a maximum error of ±4% at the extended operating temperature limits of 55°C and +125°C. All devices are available in either the hermeticallyse aled TO-100 metal can, TO-116 ceramic DIP or LCC packages. J, K and S grade chips are also available.
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE MONOLITHIC AD532
1. True ratiometric trim for improved power supply rejection. 2. Reduced power requirements since no networks across supplies are required. 3. More reliable since standard monolithic assembly techniques can be used rather than more complex hybrid approaches. 4. High impedance X and Y inputs with negligible circuit loading. 5. Differential X and Y inputs for noise rejection and additional computational flexibility.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
X2
AD532SPECIFICATIONS
Model MULTIPLIER PERFORMANCE Transfer Function Total Error (10 V X, Y +10 V) TA = Min to Max Total Error vs. Temperature Supply Rejection (± 15 V ± 10%) Nonlinearity, X (X = 20 V pk-pk, Y = 10 V) Nonlinearity, Y (Y = 20 V pk-pk, X = 10 V) Feedthrough, X (Y Nulled, X = 20 V pk-pk 50 Hz) Feedthrough, Y (X Nulled, Y = 20 V pk-pk 50 Hz) Feedthrough vs. Temperature Feedthrough vs. Power Supply DYNAMICS Small Signal BW (VOUT = 0.1 rms) 1% Amplitude Error Slew Rate (VOUT 20 pk-pk) Settling Time (to 2%, VOUT = 20 V) NOISE Wideband Noise f = 5 Hz to 10 kHz Wideband Noise f = 5 Hz to 5 MHz OUTPUT Output Voltage Swing Output Impedance (f 1 kHz) Output Offset Voltage Output Offset Voltage vs. Temperature Output Offset Voltage vs. Supply INPUT AMPLIFIERS (X, Y and Z) Signal Voltage Range (Diff. or CM Operating Diff) CMRR Input Bias Current X, Y Inputs X, Y Inputs TMIN to TMAX Z Input Z Input T MIN to TMAX Offset Current Differential Resistance DIVIDER PERFORMANCE Transfer Function (Xl > X2 ) Total Error (VX = 10 V, 10 V VZ +10 V) (VX = 1 V, 10 V VZ +10 V) SQUARE PERFORMANCE Transfer Function Total Error SQUARE ROOTER PERFORMANCE Transfer Function Total Error (0 V VZ 10 V) POWER SUPPLY SPECIFICATIONS Supply Voltage Rated Performance Operating Supply Current Quiescent PACKAGE OPTIONS TO-116 (D-14) TO-100 (H-10A) LCC (E-20A)
Specifications subject to change without notice.
(@ +25 C, VS =
AD532J Typ Max
15 V, R 2 k
M in AD532K Typ
VOS grounded)
Max M in AD532S Typ Max Units
Min
(X1 X 2 )(Y1 Y 2 ) 10 V
(X1 X 2 )(Y1 Y 2 ) 10 V
(X1 X 2 )(Y1 Y 2 ) 10 V
± 1.5 ± 2.5 ± 0.04 ± 0.05 ± 0.8 ± 0.3 50 30 2.0 ± 0.25 1 75 45 1 0.6 3.0
2.0
± 0.7 ± 1.5 ± 0.03 ± 0.05 ± 0.5 ± 0.2 30 25 1.0 ± 0.25 1 75 45 1 0.6 3.0
1.0
± 0.5
± 0.01 ± 0.05 ± 0.5 ± 0.2 100 80 30 25 1.0 ± 0.25 1 75 45 1 0.6 3.0 ± 10 30 ± 13 1 ± 2.5 ± 10 50 4 15 1.5 8 ±5 ± 25 ± 0.1 10 4
1.0 4.0 0.04
% % % / °C %/% % % mV mV mV p-p/°C mV/% MHz kHz V/µs µs mV (rms) mV (rms) V mV m V / °C mV/%
200 150
100 80
± 10
± 13 1 ± 40 0.7 ± 2.5 ± 10
± 10
± 13 1 0.7 ± 2.5 ± 10
30 2.0
40 3 10 ± 10 ± 30 ± 0.3 10 10 V Z/(X1 X2 ) ±2 ±4
(X1 X 2 ) 10 V
2
50 1.5 8 ±5 ± 25 ± 0.1 10 10 V Z/(X1 X2) ±1 ±3
(X1 X 2 ) 10 V
2
V dB µA µA µA µA µA M
15
10 V Z/(X1 X2 ) ±1 ±3
(X1 X 2 ) 10 V
2
% %
± 0.8 10 V Z ± 1.5 ± 15 4 6
± 0.4 10 V Z ± 1.0 ± 15 4 6
± 0.4 10 V Z ± 1.0 ± 15 4
%
%
± 10
18
± 10
18
± 10
± 22 6
V V mA
AD532JD AD532JH
AD532KD AD532KH
AD532SD AD532SH AD532SE/883B
Thermal Characteristics
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
H-10A: JC = 25°C/W; JA = 150°C/W E-20A: JC = 22°C/W; JA = 85°C/W D-14: JC = 22°C/W; JA = 85°C/W
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REV. B
AD532
ORDERING GUIDE CHIP DIMENSIONS AND BONDING DIAGRAM
Model AD532JD AD532JD/+ AD532KD AD532KD/+ AD532JH AD532KH AD532J Chip AD532SD AD532SD/883B JM38510/13903BCA AD532SE/883B AD532SH AD532SH/883B JM38510/13903BIA AD532S Chip
Temperature Ranges 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C 55°C to +125°C
Package Descriptions Side Brazed DIP Side Brazed DIP Side Brazed DIP Side Brazed DIP Header Header Chip Side Brazed DIP Side Brazed DIP Side Brazed DIP LCC Header Header Header Chip
Package Options D-14 D-14 D-14 D-14 H-10A H-10A D-14 D-14 D-14 E-20A H-10A H-10A H-10A
Contact factory for latest dimensions. Dimensions shown in inches and (mm).
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure 1, and the complete schematic in Figure 2. In the multiplying and squaring modes, Z is connected to the output to close the feedback around the output op amp. (In the divide mode, it is used as an input terminal.) The X and Y inputs are fed to high impedance differential amplifiers featuring low distortion and good common-mode rejection. The amplifier voltage offsets are actively laser trimmed to zero during production. The product of the two inputs is resolved in the multiplier cell using Gilbert's linearized transconductance technique. The cell is laser trimmed to obtain VOUT = (X1 X2)(Y1 Y2)/10 volts. The built-in op amp is used to obtain low output impedance and make possible self-contained operation. The residual output voltage offset can be zeroed at VOS in critical applications . . . otherwise the VOS pin should be grounded.
Figure 1. Functional Block Diagram
Figure 2. Schematic Diagram
REV. B
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