|Category||Analog & Mixed-Signal Processing => Switches & Multiplexers => Analog Switches => SPST|
|Description||Quad SPST JFET Analog Switch|
|Datasheet||Download SW06 datasheet
|Cross ref.||Similar parts: LF11333, LF13333|
FEATURES Two Normally Open and Two Normally Closed SPST Switches with Disable Switches Can Be Easily Configured as a Dual SPDT or a DPDT Highly Resistant to Static Discharge Destruction Higher Resistance to Radiation than Analog Switches Designed with MOS Devices Guaranteed RON Matching: 10% max Guaranteed Switching Speeds 500 ns max T OFF 400 ns max Guaranteed Break-Before-Make Switching Low "ON" Resistance: 80 max Low R ON Variation from Analog Input Voltage: 5% Low Total Harmonic Distortion: 0.01% Low Leakage Currents at High Temperature 100 nA max 30 nA max Digital Inputs TTL/CMOS Compatible and Independent of V+ Improved Specifications and Pin Compatible to LF-11333/13333 Dual or Single Power Supply Operation Available in Die Form
The is a four channel single-pole, single-throw analog switch that employs both bipolar and ion-implanted FET devices. The SW06 FET switches use bipolar digital logic inputs which are more resistant to static electricity than CMOS devices. Ruggedness and reliability are inherent in the SW06 design and construction technology. Increased reliability is complemented by excellent electrical specifications. Potential error sources are reduced by minimizing "ON" resistance and controlling leakage currents at high temperatures. The switching FET exhibits minimal RON variation over 20 V analog signal range and with power supply voltage changes. Operation from a single positive power supply voltage is possible. With 0 V, the analog signal range will extend from ground +32 V. PNP logic inputs are TTL and CMOS compatible to allow the SW06 to upgrade existing designs. The logic "0" and logic "1" input currents are at microampere levels reducing loading on CMOS and TTL logic.
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Symbol RON Match VA IA RON IS(OFF) ID(OFF) IS(ON)+ ID(ON) VINH VINL IINH IINL tON tOFF tONtOFF CS(OFF) CD(OFF) CD(ON)+ CS(ON) ISO(OFF) CTRON MATCH BETWEEN SWITCHES ANALOG VOLTAGE RANGE
ANALOG CURRENT RANGE RON VS. APPLIED VOLTAGE SOURCE CURRENT IN "OFF" CONDITION DRAIN CURRENT IN "OFF" CONDITION SOURCE CURRENT IN "ON" CONDITION LOGICAL "1" INPUT VOLTAGE LOGICAL "0" INPUT VOLTAGE LOGICAL "1" INPUT CURRENT LOGICAL "0" INPUT TURN-ON TIME
Full Temperature Range2, 4 Full Temperature Range2, 4 VIN 15.0 V5 VIN 0.8 V See Switching Time Test Circuit4, 6 See Switching Time Test Circuit4, 6 Note 0 VBREAK-BEFORE-MAKE TIME SOURCE CAPACITANCE DRAIN CAPACITANCE CHANNEL "ON" CAPACITANCE
5 V rms, = 7 pF, 5 V rms, = 7 pF, 500 kHz3 All Channels "OFF", DIS = "0"3 All Channels "OFF", DIS = "0"3 All Channels "ON" or "OFF"3
Conditions Operating TA = Max Operating TA = Max Operating TA = Max Operating Temp3, 9 VIN 15.0 V5 VIN 0.8 V See Switching Time Test Circuit4, 8 See Switching Time Test Circuit4, 8 Note 7 All Channels "OFF," DIS = "0"3 All Channels "OFF," DIS = "0"3 All Channels "ON" or "OFF"3RON MATCH BETWEEN SWITCHES RON Match ANALOG VOLTAGE RANGE VA IA RON
ANALOG CURRENT RANGE RON WITH APPLIED VOLTAGE SOURCE CURRENT IN "OFF" CONDITION DRAIN CURRENT IN "OFF" CONDITIONIS(OFF) ID(OFF) IS(ON)+ ID(ON) IINH IINL tON tOFF tONtOFF I+
LEAKAGE CURRENT IN "ON" CONDITION LOGICAL "1" INPUT CURRENT LOGICAL "0" INPUT CURRENT TURN-ON TIME
Guaranteed R ON and leakage tests. For normal operation maximum analog signal voltages should be restricted to less than (V+) 4 V. Switch being tested ON or OFF as indicated, V INH V or VINL 0.8 V, per logic truth table. 4 Also applies to disable pin. 5 Current tested 2.0 V. This is worst case condition. 6 Sample tested. 7 Switch is guaranteed by design to provide break-before-make operation. 8 Guaranteed by design. 9 Parameter tested only = +125°C for military grade device. Specifications subject to change without notice.
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