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Details, datasheet, quote on part number:65550
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| Part: | 65550 |
| Category: | Multimedia => Video => Controllers |
| Description: | The 65550 HiQV32TM Accelerator Product From Asiliant is a Highly Integrated Graphics/flat Panel Controller Pin Compatible With The 65545's 208 Pin PQFP Package. |
| Company: | Asiliant Technologies |
| Datasheet: | Download 65550 datasheet File size : 3946 kB |
| Request For quote: | Find where to buy 65550
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Datasheet text preview:
65550
High Performance Flat Panel/ CRT GUI Accelerator
Data Sheet Revision 1.5 October 1997
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Copyright Notice Copyright© 1997 Chips and Technologies, Inc. ALL RIGHTS RESERVED. This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language or computer language, in any form or by any means - electronic, mechanical, magnetic, optical, chemical, manual, or otherwise any part of this publication without the express written permission of Chips and Technologies, Inc. Restricted Rights Legend Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.2777013. Trademark Acknowledgment CHIPS Logo, PEAK, PRINTGINE, SCAT, and WINGINE are registered trademarks of Chips and Technologies, Inc. HiQVideo, HiQV32, HiQV64, HiQV64P, HiQVPro, HiQVDual, HiQVDualP, HiQV-MPEG, HiQV-3D, and "Solutions for a Changing World" are trademarks of Chips and Technologies, Inc. Brooktree and RAMDAC are trademarks of Brooktree Corporation. Hercules is a trademark of Hercules Computer Technology. Inmos is a trademark of Inmos Corporation. 386SX, i387, 486, i486, and Pentium are trademarks of Intel Corporation. IBM, AT, PS/2, and Personal System/2 are registered trademarks of International Business Machines Corporation, XT is a trademark of International Business Machines Corporation. Microsoft is a registered trademark of Microsoft Corporation. trademarks of Microsoft Corporation. MultiSync is a trademark of Nippon Electric Company (NEC). PanelLink technology is licensed by Chips and Technologies, Inc. from Silicon Image, Inc. in Palo Alto, CA. PanelLink is a trademark of Silicon Image, Inc. VESA is a registered trademark of Video Electronics Standards Association. VL-Bus is a trademark of Video Electronics Standards Association. Weitek is a registered trademark of Weitek Inc. All other trademarks are the property of their respective holders. Disclaimer This document provides general information for the customer. Chips and Technologies, Inc., reserves the right to modify the information contained herein as necessary and the customer should ensure that it has the most recent revision of the document. CHIPS makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. The customer should be on notice that many different parties hold patents on products, components, and processes within the personal computer industry. Customers should ensure that their use of the products does not infringe upon any patents. CHIPS respects the patent rights of third parties and shall not participate in direct or indirect patent infringement. MS-DOS and Windows are
TRI-STATE is a registered trademark of National Semiconductor Corporation.
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INTRODUCTION / OVERVIEW
65550 (HiQV32TM) TM High Performance MultiMedia Flat Panel / CRT GUI Accelerator
s Highly integrated design Flat Panel and CRT GUI Accelerator & Multimedia Engine, Palette/DAC, and Clock Synthesizer s Hardware Windows Acceleration · 64-bit Graphics Engine - System-to-Screen and Screen-to-Screen BitBLT - 3-Operand Raster-Ops - 8/16/24 Color Expansion · Transparent BLT - Optimized for WindowsTM BitBLT format s PCI Bus with Burst Mode capability and BIOS ROM support s VL-Bus and 486 Local Bus support s Flexible Memory Configurations · 32-Bit memory interface · Two or four 256Kx16 DRAMs (1MB or 2MB) · One 512Kx32 DRAMs (2MB) · Two 128Kx32 DRAMs (1MB) · Four 128Kx16 DRAMs (1MB) s High Performance: · Deep write buffers · EDO DRAM Support - 40 MHz @ 3.3V s Hardware Multimedia Support · Zoom Video port · YUV input from System Bus or Video Port · YUV-RGB Conversion · Capture / Scaling · Zoom up to 8x · Interpolation · Double Buffered Video s Display centering and stretching features for optimal fit of VGA graphics and text on 800x600 and 1024x768 panels s Simultaneous Hardware Cursor and Pop-up Window · 64x64 pixels by 4 colors · 128x128 pixels by 2 colors s Game Acceleration · Source Transparent BLT · Destination Transparent BLT · Double buffer support for YUV and 15/16bpp Overlay Engine · Instant Full Screen Page Flip · Read back of CRT Scan line counters. s Optimized for High-Performance Display at 3.3V · 640x480 x 24bpp · 800x600 x 24bpp · 1024x768 x 16bpp s CRT Support · 80 MHz @ 3.3V · 110 MHz @ 5.0V s Direct interface to Color and Monochrome, Single Drive (SS), and Dual Drive (DD), STN & TFT panels s Flexible On-chip Activity Timer facilitates ordered shut-down of the display system s Advanced Power Management feature minimizes power usage in: · Normal operation · Standby (Sleep) modes · Panel-Off Power-Saving Mode s VESA Standards supported · VAFC Port for display of "Live" Video · DPMS for CRT power-down (required for support of EPA Energy-Star program) · DDC for CRT Plug-Play & Display Control s Composite NTSC / PAL Support s Power Sequencing control outputs regulate application of Bias voltage, +5V to the panel and +12V to the inverter for backlight operation s Mixed 3.3V and 5.0V Operation s Fully Compatible with IBM® VGA Flat Panel
REVISION 1.5
12/08/97 SUBJECT TO CHANGE WITHOUT NOTICE
65550
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INTRODUCTION / OVERVIEW
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REVISION 1.5
10/14/97 SUBJECT TO CHANGE WITHOUT NOTICE
65550
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iii INTRODUCTION / OVERVIEW
System Diagrams
The 65550 system configurations appear below. Figure 1 shows the connections to external hardware:
Option I
NT S C /PA L Video Input
Video Input Module
Option II
NT S C /PA L Video Input
Video Input Module
Video De co d e r w/o Scaling
2 Meg Shared Frame Buffer
32 bit
Color STN/TFT
16 bit 24
RG B
Video De co d e r w/ Scaling
16 bit
H i Q V 32 TM
RGB to NTS C
CRT Mon i tor
PCI Bus Master
TV Mon i tor
32 Bit
32 Bit
System Bus
Figure 1: System Diagram - External Interfaces
Figure 2 shows the data flow within the chip:
M em o r y
RGB
YUVa
YUVb
32-b i t
M em ory C o n t r o lle r
H iQ V 3 2 TM
6 4 - b it G r a p h ic s E n g in e
V id eo C a p t u r e Port
S c a lin g
RGB YUV
P a th I
C a p tu re
Y U V to R G B C o lo r K e y Zoom
A n a lo g R G B D ig it a l R G B O u tp u t
Bus In te r f a c e
P C I /V L B u s
P a t h II
Figure 2: Internal Data Flow
REVISION 1.5
10/14/97 SUBJECT TO CHANGE WITHOUT NOTICE
65550
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