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Part: 5962-0325001QXC
Category:
FPGAs/PLDs
-> FPGA (Field Programmable Gate Array)
Description: Rad Hard Reprogrammable Fpga With Freeram, up to 50K Usable Gates And 18Kbit SRAM<<<>>><<<>>>Features<<<>>> Functionally And Pin Compatible With The Atmel Commercial And Military AT40K Series<<<>>> Ultra High Performance<<<>>> System Speeds 60 MHz<<<>>> Array Multipliers > 32 MHz<<<>>> 18 NS Flexible SRAM<<<>>> Internal Tri-state Capability in Each Cell<<<>>> Freeram <<<>>> Flexible, Single/dual Port, Sync/async 18 NS SRAM<<<>>> 18432 Bits of Distributed SRAM Independent of Logic Cells For AT40KEL040<<<>>> 384 Pci Compliant I/Os<<<>>> Programmable Output Drive<<<>>> Fast, Flexible Array Access Facilitates Pin Locking<<<>>> 8 Global Clocks<<<>>> Fast, Low Skew Clock Distribution<<<>>> Programmable Rising/falling Edge Transitions<<<>>> Distributed Clock Shutdown Capability For Low Power Management<<<>>> Global Reset/asynchronous Reset Options<<<>>> 4 Additional Dedicated Pci Clocks<<<>>> Cache Logic Dynamic Full/partial Reconfigurability In-System<<<>>> Unlimited Reprogrammability Via Serial or Parallel Modes<<<>>> Enables Adaptive Designs<<<>>> Enables Fast Vector Multiplier Updates<<<>>> Quick-change Tools For Fast, Easy Design Changes<<<>>> Package Options<<<>>> MQFPF160<<<>>> MQFPF256<<<>>> Industry-standard Design Tools<<<>>> Seamless Integration (Libraries, Interface, Full Back-annotation) With<<<>>>exemplar , Mentor , Synplicity <<<>>> Timing Driven Placement & Routing<<<>>> Automatic/interactive Multi-chip Partitioning<<<>>> Fast, Efficient Synthesis<<<>>> Over 75 Automatic Component Generators Create 1000s<<<>>>of Reusable, Fully Deterministic Logic And RAM Functions<<<>>> Intellectual Property Cores<<<>>> FIR Filters, Uarts, Pci, FFT And Other System Level Functions<<<>>> Easy Migration to Atmel Gate Arrays For High Volume Production<<<>>> Supply Voltage 3.3V<<<>>> 200 Krads (TM 1019.5)<<<>>> Latch-up Threshold Higher Than 70 MeV.cm2/mg<<<>>> Built-in Seu Hardening<<<>>> Quality Grades<<<>>> QML -Q And -V With SMD 5962-03250<<<>>> Escc B<<<>>> Design Tools<<<>>> Design Kit (AT40KEL-DK) Including:<<<>>>mother Board<<<>>>daughter Board For MQFPF160<<<>>>AT17 Series Configuration Memory Isp Download Cable<<<>>>system Designer Cd-rom (Including Ids Tool)<<<>>> Additional Daughter Board Variant:<<<>>>ATDH40D256M: For MQFPF256
Company: ATMEL Corporation
Datasheet: Download 5962-0325001QXC datasheet File size : 134 kB
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Features
· Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series · Ultra High Performance
System Speeds 60 MHz Array Multipliers > 32 MHz 18 ns Flexible SRAM Internal Tri-state Capability in Each Cell FreeRAM TM Flexible, Single/Dual Port, Sync/Async 18 ns SRAM 18432 Bits of Distributed SRAM Independent of Logic Cells for AT40KEL040 384 PCI Compliant I/Os Programmable Output Drive Fast, Flexible Array Access Facilitates Pin Locking 8 Global Clocks Fast, Low Skew Clock Distribution Programmable Rising/Falling Edge Transitions Distributed Clock Shutdown Capability for Low Power Management Global Reset/Asynchronous Reset Options 4 Additional Dedicated PCI Clocks Cache Logic® Dynamic Full/Partial Reconfigurability In-System Unlimited Reprogrammability via Serial or Parallel Modes Enables Adaptive Designs Enables Fast Vector Multiplier Updates Quick-ChangeTM Tools for Fast, Easy Design Changes Package Options MQFPF160 MQFPF256 Industry-standard Design Tools Seamless Integration (Libraries, Interface, Full Back-annotation) with ExemplarTM, Mentor®, Synplicity® Timing Driven Placement & Routing Automatic/Interactive Multi-chip Partitioning Fast, Efficient Synthesis Over 75 Automatic Component Generators Create 1000s of Reusable, Fully Deterministic Logic and RAM Functions Intellectual Property Cores Fir Filters, UARTs, PCI, FFT and Other System Level Functions Easy Migration to Atmel Gate Arrays for High Volume Production Supply Voltage 3.3V 200 Krads (TM 1019.5) Latch-up Threshold Higher than 70 MeV.cm 2/mg Built-in SEU Hardening Quality Grades QML -Q and -V with SMD 5962-03250 ESCC B Design Tools Design Kit (AT40KEL-DK) Including: Mother Board Daughter Board for MQFPF160 AT17 Series Configuration Memory ISP Download Cable System Designer CD-ROM (Including IDS Tool) Additional Daughter Board Variant: ATDH40D256M: for MQFPF256
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Rad Hard Reprogrammable FPGAs with FreeRAMTM
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AT40KEL040
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Table 1. AT40KEL040
Device Usable Gates Rows x Columns Cells Registers RAM Bits I/O (max) Note: 1. Packages with FCK will have 8 less clocks. AT40KEL040 40K - 50K 48 x 48 2,304 3,048(1) 2304 384
Description
The AT40KEL040 is a fully PCI-compliant, SRAM-based FPGA with distributed 18 ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and 50,000 usable gates. I/O counts range from 128 to 384 in Aerospace standard packages and support 3.3V. The AT40KEL040 is designed to quickly implement high performance, large gate count des igns through the use of synthesis and schematic-based tools used on a PC and SunTM platform. Atmel's design tools provide seamless integration with industry standard tools such as Synplicity, Modelsim, Exemplar and Viewlogic. See the IDS datasheet for other supported tools. T he AT40KEL040 can be used as a co-processor for high-speed (DSP/processorbased) designs by implementing a variety of compute-intensive, arithmetic functions. Th e se include adaptive finite impulse response (FIR) filters, Fast Fourier Transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications. The AT40KEL040 FPGA offers a patented distributed 11 - 13 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel's macro generator tool. The AT40KEL040's patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40KEL040's Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, e nab li ng vast improvement in system speed at much lower cost than conventional F P GA s . The AT40KEL040 is capable of implementing Cache Logic (Dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40KEL040 can act as a reconfigurable co-proc es s or . The AT40KEL040 FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already
Fast, Flexible and Efficient SRAM
Fast, Efficient Array and Vector Multipliers
Cache Logic Design
Automatic Component Generators
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AT40KEL040
proven functions. The Automatic Component Generators work seamlessly with industrys tan dard schematic and synthesis tools to create the fastest, most efficient designs available. The patented AT40KEL040 series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. Devices offer 50,000 usable gates, and have 3,056 registers. AT40K series FPGAs utiliz e a reliable 0.35µ single-poly, 4-metal CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based integrated development system (IDS) is used to create AT40KEL040 series designs. Multiple design entry methods are supported. T he Atmel architecture was developed to provide the highest levels of performance, f unc tional density and design flexibility in an FPGA. The cells in the Atmel array are s mall, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell's small size leads to arrays w ith large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-s peed busing network provides fast, efficient communication over medium and long distances.
AT40KEL040 Configurator
Statistics extracted from configuration bitstreams show that the maximum needed size is 1Mbit. In order to keep the maximum number of pins assigned to signals, it is recommended to use a serial configuration interface. T his is the reason why Atmel proposes a 1Mbit serial EEPROM for configuring the AT40KEL040, the AT17LV010-10DP which is also a 3.3V bias chip. It is packaged into a 28-pin DIL Flat Pack 400mils wide. This memory has been tested for total dose under bias and unbiased conditions, exhibiting far better results when unbiased; this is the reason why it is recommended to switch off the memory when it is not in the configuration mode. In addition, heavy ions tests have shown that the data stored in the memory cells are not corrupted eventhough errors may be detected while downloading the bitstream; this is the result of the data serialization from the parallel memory plan; therefore, it is recomm e n d e d to use the FPGA CRC while configuring it, and to resume the configuration when an error is detected.
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The Symmetrical Array
At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous from one edge to the other, except for bus repeaters spaced every four cells (Figure 2 on page 5) . At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM(1) , with either synchronous or asynchronous operation.
Note: 1. The right-most column can only be used as single-port RAM.
Figure 1. Symmetrical Array Surrounded by I/O
= I/O Pad = AT40K Cell
= Repeater Row = Repeater Column
= FreeRAM
Note:
AT40K has registered I/Os. Group enable every sector for tri-states on obuf's.
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AT40KEL040
Figure 2. Floorplan (Representative Portion)(1)
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= Vertical Repeater = Horizontal Repeater = Core Cell
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Note:
1. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool.
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