Details, datasheet, quote on part number: AT49BV4096AT-12TI
CategoryMemory => Flash => Parallel Flash => 4M
Description4-megabit (512k X 8/ 256k X 16) Single 2.7-volt Battery-voltage (tm) Flash Memory
CompanyATMEL Corporation
DatasheetDownload AT49BV4096AT-12TI datasheet


Features, Applications

Single-voltage Read/Write Operation: to 3.6V (BV), to 3.6V (LV) Fast Read Access Time 70 ns Internal Erase/Program Control Sector Architecture One 8K Word (16K Bytes) Boot Block with Programming Lockout Two 4K Word (8K Bytes) Parameter Blocks One 240K Word (480K Bytes) Main Memory Array Block Fast Sector Erase Time 10 Seconds Byte-by-byte or Word-by-word Programming 30 s Typical Hardware Data Protection Data Polling for End of Program Detection Low Power Dissipation 25 mA Active Current 50 A CMOS Standby Current Typical 10,000 Write Cycles


The 3-volt, 4-megabit Flash memory organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times 70 ns with power dissipation of just at 2.7V read. When deselected, the CMOS standby current is less than 50 A. The device contains a user-enabled "boot block" protection feature. The AT49BV/LV4096A locates the boot block at lowest order addresses ("bottom boot"). To allow for simple in-system reprogrammability, the AT49BV/LV4096A does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV4096A is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis.

Pin Name OE WE RESET VPP I/O15 I/O15(A-1) BYTE NC Function Addresses Chip Enable Output Enable Write Enable Reset VPP can be left unconnected or connected to VCC, GND, or 12V. The input has no effect on the operation of the device. Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect

The device is erased by executing the Erase command sequence; the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections, the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles. The 8K word boot block section includes a reprogramming lock out feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 5.5 volts or less are used. The boot sector is designed to contain user secure code. The BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic "1" or left open, the device is in word configuration, - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic "0", the device is in byte configuration, and only data I/O pins - I/O7 are active and controlled by CE and OE. The data I/O pins - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function.


READ: The AT49BV/LV4096A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state whenever OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the or CE input with or WE low (respectively) and OE high. The address is latched on the falling edge CE or WE, whichever occurs last. The data is latched by the first rising edge CE or WE. Standard microprocessor write


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