Details, datasheet, quote on part number: AT49BV512-15JC
CategoryMemory => Flash
Description512k (64kx8) Single 2.7v Battery-voltage (tm) Flash Memory
CompanyATMEL Corporation
DatasheetDownload AT49BV512-15JC datasheet
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Features, Applications

Single Supply Voltage Range, to 3.6V Single Supply for Read and Write Fast Read Access Time 70 ns Internal Program Control and Timer 8K Bytes Boot Block with Lockout Fast Erase Cycle Time 10 Seconds Byte-by-Byte Programming 30 s/Byte Typical Hardware Data Protection DATA Polling for End of Program Detection Low Power Dissipation 25 mA Active Current 50 A CMOS Standby Current Typical 10,000 Write Cycles


The a 3-volt only, 512K Flash memories organized as 65,536 words of 8 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 A. To allow for simple in-system reprogrammability, the AT49BV512 does not require high input voltages for programming. Three-volt only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV512 is performed by erasing

Pin Name I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect

the entire 1 megabit of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.


READ: The AT49BV512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 64K bytes memory array (or 56K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical on a byte-by-byte basis. Please note that a data " 0" cannot be programmed back a "1"; only erase operations can convert to "1"s. Programming is accomplished via the internal device command register and a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge WE or CE, whichever occurs last, and the data latched on the rising edge WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block to 1FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data I/O0 is low, the boot block can be programmed; if the data I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49BV512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV512 in the following ways: (a) VCC sense: CC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with to 3.6V power supply, the address inputs and control inputs ( OE, CE and WE) may be driven from to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.


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