Details, datasheet, quote on part number: AT49BV8192T-20RC
PartAT49BV8192T-20RC
CategoryMemory
Description8-megabit 512k X 16 CMOS Flash Memory
CompanyATMEL Corporation
DatasheetDownload AT49BV8192T-20RC datasheet
  

 

Features, Applications
Features

2.7V Read 5V Program/Erase Fast Read Access Time 120 ns Internal Erase/Program Control Sector Architecture One 8K Words (16K bytes) Boot Block with Programming Lockout Two 8K Words (16K bytes) Parameter Blocks One 488K Words (976K bytes) Main Memory Array Block Fast Sector Erase Time - 10 seconds Word-By-Word Programming - 30 s/Word Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation 25 mA Active Current 50 A CMOS Standby Current Typical 10,000 Write Cycles

Description

The AT49BV8192 and AT49LV8192 are 3-volt, 8-megabit Flash Memories organized as 512K words of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times 120 ns with power dissipation of just at 2.7V read. When deselected, the CMOS standby current is less than 50 A. (continued)

Pin Name OE WE RESET VPP I/O15 NC Function Addresses Chip Enable Output Enable Write Enable Reset Program/Erase Power Supply Data Inputs/Outputs No Connect TSOP Top View Type 1

The device contains a user-enabled "boot block" protection feature. Two versions of the feature are available: the AT49BV/LV8192 locates the boot block at lowest order addresses ("bottom boot"); the AT49BV/LV8192T locates it at highest order addresses ("top boot") To allow for simple in-system reprogrammability, the AT49BV/LV8192 does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV8192 is performed by first erasing a block of data and then programming on a word-by-word basis. The device is erased by executing the erase command sequence; the device internally controls the erase operation. The memory is divided into three blocks for erase operations. There are two 8K word parameter block sections and one sector consisting of the boot block and the

main memory array block. The AT49BV/LV8192 is programmed on a word-by-word basis. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 3.6 volts or less are used. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K word boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. During a chip erase, sector erase, or word programming, the VPP pin must 10%.

INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING MAIN MEMORY (488K WORDS) PARAMETER BLOCK 2 8K WORDS PARAMETER BLOCK 1 8K WORDS BOOT BLOCK 8K WORDS

INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING
BOOT BLOCK 8K WORDS PARAMETER BLOCK 1 8K WORDS PARAMETER BLOCK 2 8K WORDS MAIN MEMORY (488K WORDS)

READ: The AT49BV/LV8192 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low 2 pulse on the or CE input with or WE low (respectively) and OE high. The address is latched on the falling edge CE or WE, whichever occurs last. The data is latched by the first rising edge CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the Read or Standby mode, depending upon the state of the control inputs. By applying 0.5V input

signal to the RESET pin the boot block array can be reprogrammed even if the boot block program lockout feature has been enabled (see Boot Block Programming Lockout Override section). ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands. CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erease the chip is tEC. If the boot block lockout has been enabled, the Chip Erase will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into three sectors that can be individually erased. There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array block. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). Once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical on a word-byword basis. Programming is accomplished via the internal device command register and a 4 bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back a "1"; only erase operations can convert to "1"s. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the 49BV/LV8192 boot block to 01FFFH while the address range of the to 7FFFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels 5.5V or less are used. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data I/O0 is low, the boot block can be programmed; if the data I/O0 is high, the program lockout feature has been enabled and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts during the entire chip erase, sector erase or word programming operation. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV/LV8192 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA polling may begin at any time during the program cycle.


 

Related products with the same datasheet
AT49BV8192T-12RC
AT49BV8192T-12RI
AT49BV8192T-12TC
AT49BV8192T-12TI
AT49BV8192T-15RC
AT49BV8192T-15RI
AT49BV8192T-15TC
AT49BV8192T-15TI
AT49BV8192T-20RI
AT49BV8192T-20TC
AT49BV8192T-20TI
Some Part number from the same manufacture ATMEL Corporation
AT49BV8192T-20RI 8-megabit 512k X 16 CMOS Flash Memory
AT49F001 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001-12JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001-55 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001-55JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001-70 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001-70JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001-90 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001-90JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001N 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001N-12JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001N-55 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001N-55JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001N-70 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001N-70JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001N-90 128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
AT49F001N-90JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby
AT49F001NT 1-megabit (128kx8) 5v Only CMOS Flash Memory
AT49F001NT-12JC 1-Megabit (128K X 8) 5-volt Only Flash Memory, 50mA Active, 0.1mA Standby

AT17C256-10I : FPGA/PLD Configuration Memory Fpga Configuration EePROM Memory 64k, 128k And 256k

AT27C1024-55C : ->UV/EPROM 1-mb (64kx16) OTP EPROM

AT28C16-15PC : 16k (2kx8) Parallel EePROMs

AT49F516 : 512k 5-volt Only Flash Memory: 32kx16

ATF1502SE-5AC44 : Second Generation Industry Compatible 5V Logic Doubling CPLDS 32 Macrocells, Standard Power W/isp

TSC80C51XXX-40MA/883 : CMOS Single-chip 8 Bit Microcontroller, 4Kx8 Mask ROM, 128 Bytes of RAM, 32 I/o Lines, 16 Bit Timers, 40 MHZ

ATAM510 : Marc4 4-bit MTP Universal Microcontroller

U490B-M : Pmic - Power Management - Specialized Integrated Circuit (ics) Tube 2mA 7.2 V ~ 9.2 V; IC PHASE CONTROL ONE-SHOT 8-DIP Specifications: Applications: Electric Stapler Devices ; Current - Supply: 2mA ; Voltage - Supply: 7.2 V ~ 9.2 V ; Package / Case: 8-DIP (0.300", 7.62mm) ; Packaging: Tube ; Operating Temperature: -10C ~ 100C ; Lead Free Status: Contains Lead ; RoHS Status: RoHS Non-Compliant

AT87LV55-12JC : 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQFP44 Specifications: Data Bus: 8 Bit ; Life Cycle Stage: ACTIVE ; Clock Speed: 12 MHz ; ROM Type: OTP ; Supply Voltage: 2.7 to 5.5 volts ; I/O Ports: 32 ; Package Type: TQFP, Other, 1 MM HEIGHT, PLASTIC, TQFP-44 ; Operating Range: Commercial ; Pin Count: 44 ; Operating Temperature: 0 to 70 C (32 to 158 F

 
0-C     D-L     M-R     S-Z