Details, datasheet, quote on part number: AT49F001-12C
PartAT49F001-12C
CategoryMemory => Flash
Description128K X 8 (1M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash
CompanyATMEL Corporation
DatasheetDownload AT49F001-12C datasheet
  

 

Features, Applications
Features

5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes Parameter Blocks Two Main Memory Blocks (32K, 64K Bytes) Fast Erase Cycle Time 10 Seconds Byte-by-byte Programming 10 s/Byte Typical Hardware Data Protection DATA Polling for End of Program Detection Low Power Dissipation 50 mA Active Current 100 A CMOS Standby Current Typical 10,000 Write Cycles

Description

The a 5-volt only in-system reprogrammable Flash memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to

Pin Name OE WE RESET NC DC Function Addresses Chip Enable Output Enable Write Enable RESET Data Inputs/Outputs No Connect Don't Connect

55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A. For the AT49F001N(T) pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package are don't connect pins. To allow for simple in-system reprogrammability, the AT49F001(N)(T) does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F001(N)(T) is performed by erasing a block of data and then programming on a byte-bybyte basis. The byte programming time is a fast 50 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K bytes parameter block sections and two main memory blocks. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16-Kbyte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. In the AT49F001(N)(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49F001(T), once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less.

AT49F001(N) DATA INPUTS/OUTPUTS - I/O0 VCC GND WE CE RESET 8 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 1FFFF X DECODER MAIN MEMORY BLOCK 2 (64K BYTES) MAIN MEMORY BLOCK 1 (32K BYTES) PARAMETER BLOCK 2 (8K BYTES) PARAMETER BLOCK 1 (8K BYTES) BOOT BLOCK (16K BYTES) BOOT BLOCK (16K BYTES) 10000 0FFFF PARAMETER BLOCK 1 (8K BYTES) PARAMETER BLOCK 2 (8K BYTES) MAIN MEMORY BLOCK 1 (32K BYTES) MAIN MEMORY BLOCK 2 (64K BYTES) AT49F001(N)T DATA INPUTS/OUTPUTS I/O0 8 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 1C000 1BFFF

READ: The AT49F001(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the or CE input with or WE low (respectively) and OE high. The address is latched on the falling edge CE or WE, whichever occurs last. The data is latched by the first rising edge CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high inpendance state. If the RESET pin makes a high-to-low transition during a program or erase operation, the operation may not be successfully completed and the operation will have to be repeated after a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available for the AT49F001N(T). ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored.


 

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