Details, datasheet, quote on part number: ATF2500CL
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD) => Other Families
TitleEE Programmable SPLD
DescriptionHigh-speed Programmable Logic Device
CompanyATMEL Corporation
DatasheetDownload ATF2500CL datasheet
Find where to buy


Features, Applications

High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 15 ns Maximum Pin-to-pin Delay for 5V Operation 24 Flexible Output Macrocells 48 Flip-flops Two per Macrocell 72 Sum Terms All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops Product Term or Direct Input Pin Clocking Registered or Combinatorial Internal Feedback Backward Compatible with ATV2500B/BQ and ATV2500H Software Advanced Electrically-erasable Technology Reprogrammable 100% Tested 44-lead Surface Mount Package and DIP Package Flexible Design: to 48 Buried Flip-flops and 24 Combinatorial Outputs Simultaneously 8 Synchronous Product Terms Individual Asynchronous Reset per Macrocell OE Control per Macrocell Functionality Equivalent to ATV2500B/BQ and ATV2500H 2000V ESD Protection Security Fuse Feature to Protect the Code Commercial and Industrial Temperature Range Offered 10 Year Data Retention Pin Keeper Option 200 mA Latch-up Immunity

Pin Name IN CLK/IN I/O 0,2,4... I/O 1,3,5... GND VCC Function Logic Inputs Pin Clock and Input Bi-directional Buffers "Even" I/O Buffers "Odd" I/O Buffers Ground +5V Supply

(PLCC/LCC/JLCC packages) pin 4 and pin 26 GND connections are not required, but are recommended for improved noise immunity.


The ATF2500C is the highest-density PLD available a 44-pin package. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The is a high-performance CMOS (electrically-erasable) programmable logic device (PLD) that utilizes Atmel's proven electrically-erasable technology. The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell's three sum terms can be combined to provide to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flipflops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.

The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF2500Cs key features are: Fully Connected Logic Array Each array input is always available to every product term. This makes logic placement a breeze. Selectable D- and T-Type Registers Each ATF2500C flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. Buried Combinatorial Feedback Each macrocell's Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources. Selectable Synchronous/Asynchronous Clocking Each of the ATF2500Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. A Total of 48 Registers The ATF2500C provides two flip-flops per macrocell a total of 48. Each register has its own clock and reset terms, as well as its own sum term. Independent I/O Pin and Feedback Paths Each I/O pin on the ATF2500C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O's output enable, facilitate true bi-directional I/O design. Combinable Sum Terms Each output macrocell's three sum terms may be combined into a single term. This provides a fan to 12 product terms per sum term with no speed penalty. Programmable Pin-keeper Circuits These weak feedback latches are useful for bus interfacing applications. Floating pins can be set to a known state if the Pin-keepers are enabled. User Row (64 bits) Use to store information such as unit history.

The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during tPR.

Description Power-up Reset Time Power-up Reset Voltage
Level Forced on Odd I/O Pin during PRELOAD Cycle VIH/V IL VIH/V IL VIH/V IL VIH/V IL


Related products with the same datasheet
Some Part number from the same manufacture ATMEL Corporation
ATF2500CQ High-speed Programmable Logic Device
ATF750C High-speed Complex Programmable Logic Device
ATFS05 Configuration Memory Used to Load The Bitstream For AT94K05AL Fpslic Devices.
ATFV2500C High Speed Programmable Logic Device
ATL25 The ATL25 Series Gate Array And Embedded Array Families From Atmel Are Fabricated on a 0.25 Micron CMOS Process With 5 Levels of Metal. This Family Features Arrays With up to 6.9 Million Routable Gates
ATL25Series Gate Array/embedded Array
ATL35 The ATL35 Series Asic Family is Fabricated on a 0.35 Micron CMOS Process With up to Four Levels of Metal. This Family Features Arrays With up to 2.7 Million Routable Gates And 976 Pins. The High Density

AT24C16SC-09ET : Smart Card/Secure Card 2-wire Serial EePROM Smart Card Modules 16k (2048 X 8)

AT27C512R-20M : ->UV/EPROM 512k (64kx8) OTP EPROM

AT40K20-2EQC : SRAM-based FPGA/PAL At40k Fpgas With Freeram(tm)

AT49BV002A-70PC : 256K X 8 (2M Bit), 2.7-Volt Read And 2.7-Volt Write, Bottom Boot Parametric Block Flash

AT49F002N-90JC : 256K X 8 (2M Bit), 5-Volt-Only, Bottom Boot Parametric Block Flash

AT49LV8192-20TC : 8-megabit 512k X 16 CMOS Flash Memory

AT87F55WD-24JC : 8051 Architecture 80C32 Microcontroller With 20K OTP Quickflash

TSS463B_03 : VAN Data Link Controller with Serial Interface

ATTINY1634-SUR : 8-BIT, FLASH, 6 MHz, RISC MICROCONTROLLER, PDIP8 Specifications: Life Cycle Stage: ACTIVE ; Clock Speed: 6 MHz ; ROM Type: Flash ; Supply Voltage: 4 to 5.5 volts ; I/O Ports: 6 ; Package Type: CDIP, Other, 0.300 INCH, PLASTIC, MS-001BA, DIP-8 ; Operating Range: Industrial ; Pin Count: 8 ; Operating Temperature: -40 to 85 C (-40 to 185 F)

TS87C51RD2-EBD : 8-BIT, OTPROM, MICROCONTROLLER, PDIP40 Specifications: Data Bus: 8 Bit ; Life Cycle Stage: ACTIVE ; ROM Type: OTP ; I/O Ports: 32 ; Package Type: CDIP, Other, PLASTIC, DIP-40 ; Pin Count: 40 ; Features: PWM

5962R01B0108VTB : FPGA, QFP352 Specifications: Package Type: QFP, Other, QFP-352 ; Logic Family: CMOS ; Pins: 352 ; Operating Temperature: -55 to 125 C (-67 to 257 F) ; Supply Voltage: 2.5V

0-C     D-L     M-R     S-Z