Details, datasheet, quote on part number: ATF750C-10JI
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD) => EE Programmable CPLD
TitleEE Programmable CPLD
DescriptionHigh-speed Complex Programmable Logic Device
CompanyATMEL Corporation
DatasheetDownload ATF750C-10JI datasheet
Cross ref.Similar parts: PAL16L8A, PAL16L8A-2, PAL16L8A-2M, PAL16L8AM, PAL16R4A, PAL16R4A-2M, PAL16R4AM, PAL16R6A, PAL16R6AM, PAL16R8A
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Features, Applications
Advanced, High-speed, Electrically-erasable Programmable Logic Device

Superset 22V10 Enhanced Logic Flexibility Backward Compatible with ATV750B/BL and ATV750/L Low-power Edge-sensing "L" Option with 1 mA Standby Current D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 7.5 ns Maximum Pin-to-pin Delay with 5V Operation Highest Density Programmable Logic Available in 24-pin Package Advanced Electrically-erasable Technology Reprogrammable 100% Tested Increased Logic Flexibility 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility All 20 Flip-flops Feed Back Internally 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles


The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform predictable delays

Pin Name CLK IN I/O GND VCC Note: Function Clock Logic Inputs Bi-directional Buffers Ground +5V Supply For PLCC, pins 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. DIP/SOIC/TSSOP

guarantee fast in-system performance. The is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel's proven electrically-erasable technology. Each of the ATF750C(L)'s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum

terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The is a low-power device with speeds as fast as 15 ns. The ATF750C(L) provides the optimum low-power CPLD solution. This device significantly reduces total system power, thereby allowing batterypowered operations.

Temperature Under Bias................................ to +125C Storage Temperature..................................... to +150C Voltage on Any Pin with Respect to +7.0V(1) Voltage on Input Pins with Respect to Ground During to +14.0V(1) Note: Programming Voltage with Respect +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.

All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to be either 10%.

5V Operation Operating Temperature (Ambient) VCC Power Supply Commercial 5V =5% Industrial 5V =10%



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