Details, datasheet, quote on part number: ATF750LVC-15SC
CategoryFPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD) => Other Families
TitleOther Families
CompanyATMEL Corporation
DatasheetDownload ATF750LVC-15SC datasheet
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Features, Applications
to 3.6V Operating Range Advanced, High-speed, Electrically-erasable Programmable Logic Device

­ Superset 22V10 ­ Enhanced Logic Flexibility ­ Architecturally Compatible with ATV750B and ATV750 Software and Hardware D- or T-type Flip-flop Product Term or Direct Input Pin Clocking 15 ns Maximum Pin-to-pin Delay with 3V Operation Highest Density Programmable Logic Available in 24-pin Package ­ Advanced Electrically-erasable Technology ­ Reprogrammable ­ 100% Tested Increased Logic Flexibility ­ 42 Array Inputs, 20 Sum Terms and 20 Flip-flops Enhanced Output Logic Flexibility ­ All 20 Flip-flops Feed Back Internally ­ 10 Flip-flops are also Available as Outputs Programmable Pin-keeper Circuits Dual-in-line and Surface Mount Package in Standard Pinouts Commercial and Industrial Temperature Ranges 20-year Data Retention 2000V ESD Protection 1000 Erase/Write Cycles


The Atmel "750" architecture is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. The is a high-performance

Pin Name CLK IN I/O GND VCC Note: Function Clock Logic Inputs Bi-directional Buffers Ground 3V Supply For PLCC, pins 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.

CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel's proven electrically-erasable technology. Each of the ATF750LVC's 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product

terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.

Temperature Under Bias.................................. to +85°C Storage Temperature..................................... to +150°C Voltage on Any Pin with Respect to +4.6V(1) Voltage on Input Pins with Respect to Ground During to +14.0V(1) Note: Programming Voltage with Respect +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 4.6V for pulses of less than 20 ns.

3.3V Operation Operating Temperature (Ambient) VCC Power Supply Commercial - 3.6V Industrial 3.0 -=3.6V


All input and I/O pins on the ATF750LVC(L) have programmable "pin-keeper" circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the software compiler table for more details. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os. Table 1. Software Compiler Mode Selection

Synario ATF750LVC (PPK) Wincupl V750C V750CPPK Pin-keeper Circuit Disabled Enabled


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